MK68564 datasheet(2/46 Pages) STMICROELECTRONICS

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SIO PIN DESCRIPTION

GND :

Ground

VCC:

+ 5 Volts (

± 5%)

CS :

Chip Select (input, active low). CS is used to select the MK68564 SIO for accesses to

the internal registers. CS and IACK must not be asserted at the same time.

R/W :

Read/write (input). R/W is the signal from the bus master, indicating wether the current

bus cycle is a Read (high) or Write (low) cycle.

DTACK :

Data Transfer Acknowledge (output, active low, three stateable). DTACK is used to

signal the bus master that data is ready or that data has been accepted by the

MK68564 SIO.

A1-A5 :

Address Bus (inputs). The address bus is used to select one of the internal registers

during a read or write cycle.

D0-D7

Data Bus (bidirectional, threee-stateable). The data bus is used to transfer data to or

from the internal registers during a read or write cycle. It is also used to pass a vector

during an interrupt acknowledge cycle.

CLK :

Clock (input). This input is used to provide the internal timing for the MK68564 SIO.

RESET :

Device Reset (input, active low). RESET disables both receivers and transmitters, forces

TxDA and TxDB to a marking condition, forces the modem controls high and disables

all interrupts. With the exception of the status registers, data registers, and the vector

INTR :

Interrupt Request (output, active low, open drain). INTR is asserted when the MK68564

SIO is requesting an interrupt. INTR is negated during an interrupt acknowledge cycle

or by clearing the pending interrupt(s) through software.

IACK :

Interrupt acknowledge (input, active low). IACK is used to signal the MK68564 SIO that

the CPU is acknowledging an interrupt. CS and IACK must not be asserted at the same

time.

IEI :

Interrupt Enable In (input, active low). IEI is used to signal the MK68564 SIO that no

higher priority device is requesting interrupt service.

IEO :

Interrupt Enable Out (output, active low). IEO is used to signal lower priority peripherals

that neither the MK68564 SIO nor another higher priority peripheral is requesting

interrupt service.

XTAL1, XTAL2 :

Baud Rate Generator inputs. A crystal may be connected between XTAL1 and XTAL2,

or XTAL1 may be driven with a TTL level clock. When using a crystal, external

capacitors must be connectd. When driving XTAL1 with a TTL level clock, XTAL2 must

be allowed to float.

RxRDYA, RxRDYB:

Receiver Ready (outputs, active low). Programmable DMA output for the receiver. The

RxRDY pins pulse low when a character is available in the receive buffer.

TxRDYA, TxRDYB :

Transmitter Ready (outputs, active low). Programmable DMA output for the transmitter.

The TxRDY pins pulse low when the transmit buffer is empty.

CTSA, CTSB :

Clear to Send (inputs, active low). If Tx Auto Enables is selected, these inputs enable

the transmitter of their respective channels. If Tx Auto Enables is not selected, these

inputs may be used as general purpose input pins. The inputs are Scmit-trigger

buffered to allow slow rise-time input signals.

DCDA, DCDB :

Data Carrier Detect (inputs, active low). If Rx Auto Enables is selected, these inputs

enable the receiver of their respective channels. If Rx Auto Enables is not selected,

these inputs may be used as general purpose input pins. The inputs are Schmit-trigger

buffered to allow slow rise-time input signals.

RxDA, RxDB :

Receive Data (inputs, active high). Serial data input to the receiver.

TxDA, TxDB :

Transmit Data (outputs, active high). Serial data output of the transmitter.

MK68564

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