MK68564 datasheet(21/46 Pages) STMICROELECTRONICS

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receive data stream that match the byte loaded into

Sync Word Register 1 will be inhibited from loading

into the receive data FIFO. The comparison be-

tween Sync Word Register 1 and the incoming data

occurs at a character boundary time. This is an 8-bit

comparison, regardless of the bits per character pro-

grammed. CRC calculations will be performed on all

bytes, even if the characters are not transferred to

the receive data FIFO, as long as the Rx CRC En-

able bit is set.

Data Transfer and Status Monitiring. After char-

acter synchronization is achieved, the assembled

characters are transferred to the receive data FIFO,

and the status information for each character is

transferred to the receive error FIFO. The following

four modes are available to transfer the received da-

ta and its associated status to the CPU.

No Receive Interrupts Enabled. This mode is used

either for polling operations or for off-line conditions.

When transferring data, using a polling routine, the

Rx Character Available bit in Status Register 0

should be checked to determine if a receive charac-

ter is available for transfer. Only when a character

is available should the receive buffer and Status Re-

gister 1 be read. The Rx Character Available bit is

set when a character is loaded to the top of the re-

ceive data FIFO. This bit is reset during a read of the

receive buffer.

Interrupt On First Character Only. This interrupt

mode is normally used to start a DMA transfer rou-

tine or, in some cases, a polling loop. The SIO will

generate an interrupt the first time a character is shif-

ted to the top of the receive data FIFO after this

mode is selected or reinitialized. An interrupt will be

generated thereafter only if a Special Receive

Condition is detected. This mode is reinitialized with

the Enable Interrupt On Next Receive Character

command. Parity Errors do not cause interrupts in

this mode ; however, a Receive Overrun Error will.

Interrupt On Every Character. This interrupt mode

will generate a Receiver Interrupt every time a char-

acter is shifted to the top of the receive data FIFO.

A Special Receive Condition interrupt on a parity er-

ror is optional in this mode.

Special Receive Condition Interrupt. The special

condition interrupt mode is not an interrupt mode as

such, but works in conjunction with Interrupt On E-

very Character or Interrupt On First Character Only

modes. When the Status Affects Vector bit in either

channel is set, a Special Receive condition will mo-

dify the Receive Interrupt vector to signal the CPU

of the special condition. Receive Overrun Error and

Parity Error are the only Special Receive Conditions

in Synchronous receive mode. The overrun and pa-

rity error status bits in Status Register 1 are latched

when they occur ; they will remain latched until an

Error Reset command is issued. As long as either

one of these bits is set, a Special Receive Condition

Interrupt will be generated at every character avai-

lable time. Since these two status bits are latched,

the error status in Status Register 1, when read, will

reflect an error in the current word in the receive buff-

er, in addition to any Parity or Overrun errors recei-

ved since the last Error Reset command.

CRC Error Checking and Receiver Message Ter-

mination. A CRC error check on the received

message can be performed on a per character

basis under program control. The Rx CRC En-

able bit must set/reset by the program before

the next character is transferred from the receive

shift register to the receive data FIFO. This ensures

proper inclusion or exclusion of data characters in

the CRC check.

There is an 8-bit delay between the time a character

is transferred to the receive data FIFO and the time

the same character starts to enter the CRC checker.

An additional 8-bit times are needed to perform CRC

calculations on the character. Due to this serial na-

ture of CRC calculations, the Receive Clock (RxC)

must cycle 16 times after the second CRC character

has been loaded into the receive data FIFO or

20 times (the previous 16 plus 3-bit buffer delay

and 1-bit input delay) after the last bit is at the

RxD input, before CRC calculation is complete.

The CRC Framing Error bit in Status Register 1

will contain the comparison results of the CRC

checker. The comparison results should be zero,

indicating error-free transmission. The results in the

status bit are valid only at the end of CRC cal-

culation. If the result is examined before this time, it

usually indicates an error (the bit is High). The

comparison is made at each character available

time and is valid until the character is read from the

receive data FIFO.

SDLC/HDLC OPERATION

INTRODUCTION

The MK68564 SIO is capable of handling both High-

level Synchronous Data Link Control (HDLC) and

IBM Synchronous Data Link Control (SDLC) proto-

cols. In the following discussion, only SDLC is ref-

erenced because of the high degree of similarity

between SDLC and HDLC.

The SDLC mode is considerably different from

Monosync and Bisync protocols, because it is bit o-

riented rather than character oriented. Bit orienta-

tion makes SDLC a flexible protocol in terms of mes-

MK68564

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