MK68901 datasheet(13/33 Pages) STMICROELECTRONICS

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A is reprogrammed for another mode, interrupts will

again occur on the transition, as normally defined by

the edge bit. Note that, like changing the edge bit,

placing the timer into or taking it out of the pulse

width mode can produce a transition on the signal

to the interrupt channel and may cause an interrupt.

If measuring consecutive pulses, it is obvious that

one must read the contents of the timer and then rei-

nitialize the main counter by writing to the timer data

pulse is going to the active state, the write operation

may result in an indeterminate value being written

into the main counter. If the timer is written after the

pulse goes active, the timer counts from the pre-

vious contents, and when it counts through H”01”,

the correct value is written into the timer. The pulse

width then includes counts from before the timer

was reloaded.

In the event count mode, the prescaler is disabled.

Each time the control input on TAI or TBi makes an

active transition as defined by the associated Inter-

rupt Channel’s edge bit, a count pulse will be gene-

rated, and the main counter will decrement. In all o-

ther respects, the timer functions as previously des-

cribed. Altering the edge bit while the timer is in the

event count mode can produce a count pulse. The

interrupt channel associated with the input (I3 for I4

for TAI) is allowed to function normally. To count

transitions reliably, the input must remain in each

state (1/O) for a length of time equal to four periods

of the timer clock ; thus signals of a frequency up to

one fourth of the timer clock can be counted.

The manner in which the timer output pins toggle

states has previously been described. All timer out-

puts will be forced low by a device RESET. The out-

put associated with Timers A and B will toggle on

each Time Out pulse regardless of the mode the ti-

mers are programmed to. In addition, the outputs

from Timers A and B can be forced low at any time

by writing a ”1” to the reset location in TACR and

TBCR, respectively. The output will be forced to the

low state during the WRITE operation, and at the

conclusion of the operation, the output will again be

free to toggle each time a Time Out pulse occurs.

This feature will allow waveform generation.

During reset, the Timer Data Registers and the main

counters are not reset. Also, if using the reset option

on Timers A or B, one must make sure to keep the

other bits in the correct state so as not to affect the

operation of Timers A and B.

USART

Serial Communication is provided by a full-duplex

double-buffered USART, which is capable of either

asynchronous or synchronous operation. Variable

word length and start/stop bit configurations are

available under software control for asynchronous

operation. For synchronous operation, a Sync Word

is provided to establish synchronization during re-

ceive operations. The Sync Word will also be repea-

tedly transmitted when no other data is available for

transmission. Moreover, the MK68901 allows strip-

ping of all Sync Words received in synchronous o-

peration. The handshake control lines RR (Receiver

Ready) and TR (Transmitter Ready) allow DMA o-

peration. Separate receive and transmit clocks are

available, and separate receive and transmit status

and data bytes allow independent operation of the

transmit and receive sections.

The USART is provided with three Control/Status

Registers and a Data Register. The USART Data

grammer may specify operational parameters for

the USART via the Control Register, as shown in fig-

ure 17. Status of both the Receiver and Transmitter

sections is accessed by means of the two Status Re-

gisters, as shown in figures 18 and 19. Data written

to the Data Register is passed to the transmitter,

while reading the Data Register will access data re-

ceived by the USART.

Figure 16 : USART Data Register.

V000362

MK68901

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