MK68901 datasheet(18/33 Pages) STMICROELECTRONICS

18 / 33 page

Figure 20 : SYNC Character Register.

Enable (XE) is set will alter the output

state until END is false. These bits should

be set prior to enabling the transmitter.

The state of these bits determine the

state of the first transmitted character af-

ter the transmitter is enabled. If the high

impedance mode was selected prior to

the transmitter being enabled, the first bit

transmitted is indeterminate.

XE :

Transmitter Enable. This control bit is u-

sed to enable or disable the transmitter.

When set, the transmitter is enabled.

When cleared, the transmitter will be di-

sabled. If disabled, any word currently in

the output register will continue to be

transmitted when XE is cleared, the

transmitter will turn off at the end of the

break character boundary, and no end of

break stop bit is transmitted. The transmit

clock must be running before the trans-

mitter is enabled A ”one” bit always pre-

cedes the first word out of the transmitter

after the transmitter is enabled. There is

a delay between the time the transmitter

enable bit is written an when the transmit-

ter reset goes low ; therefore, the H & L

bits should be written with the desired

state prior to enabling the transmitter.

Like the receiver section, there are two separate in-

terrupt channels associated with the transmitter.

The buffer Empty condition causes an interrupt via

one channel, while the Underrun and END condi-

tions will cause an interrupt via the second channel.

When underrun occurs in the synchronous format,

the character in the SCR will be transmitted until a

new words is loaded into the transmit buffer. In the

asynchronous format, a ”Mark” will be continuously

transmitted when underrun occurs.

The transmit buffer can be loaded prior to enabling

the transmitter. When the transmitter is disabled,

any character currently in the process of being trans-

mitted will continue to conclusion, but any character

in the transmit buffer will not be transmitted and will

remain in the buffer. Thus no buffer empty interrupt

will occur nor will the BE flag be ste. If the buffer were

already empty, the BE flag would be set and would

remain set. When the transmitter is disabled with a

character in the output register but with no character

in the transmit buffer, an Underrun Error will not oc-

cur when the character in progress concludes.

Often it is necessary to send a break for some par-

ticular period. To aid in timing a break transmission,

a transmission, a transmit error interrupt will be ge-

nerated at every normal character boundary time

during a break transmission. The status register in-

formation is unaffected by this error condition inter-

rupt. It should be noted that an underrun error, if pre-

sent, must be cleared from the TSR, and the inter-

rupt pending register must be cleared of pending

transmitter errors at the beginning of the break

transmission or no interrupts will be generated at the

character boundary time.

It the synchronous format is selected, the sync char-

acter should be loaded into the Sync Character Re-

gister (SCR) as shouwn in figure 20. This character

is compared to the received serial data during a

Search, and will be continuously transmitted during

an underrun condition.

All flags in the RSR or TSR will continue to function

as described whether their associated interrupt

channel is disabled or enabled. All interrupt chan-

nels are edge triggered and, in many cases, it is the

actual output of a flag bit or flag bits which is coupled

to the interrupt channel. thus, if a normal interrupt

producing condition occurs while the interrupt chan-

nel is disabled, no interrupt would be produced even

if the channel was subsequently enabled, because

a transition did not occur while the interrupt channel

was enabled. that particular flag bit would have to

occur a second time before another ”edge” was pro-

duced, causing an interrupt to be generated.

Error conditions in the USART are determined by

monitoring the Receive Status Register and the

Transmitter Status Register. These error conditions

are only valid for each word boundary and are not

latched. When executing block tranfers or data, it is

necessary to save any errors so that they can be

checked at the end of a block. In order to save error

conditions during data transfer, the MK68901 MFP

interrupt controller may be used by enabling error in-

terrupt for the desired channel (Receive error or

Transmit error) and by masking these bits off. Once

the tranfer is complete, the Interrupt Pending Regis-

ter can be polled, to determine the precence of a

pending error interrupt, and therefore an error.

V000366

MK68901

18/33

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