Operation
PCI Bus Interface
The PCI bus is a high speed alternative to ISA bus, it has been designed to overcome some of the
limitations of ISA bus, and provide faster throughput for I/O intensive peripheral devices. PCI bus
also supports Plug and Play configuration which allows the system software to allocate resources
during initialisation helping to overcome resource conflicts, which might exist in a system.
The APCI-IB40 uses a single chip PCI bus slave controller which is designed and manufactured by
PLX Technology. This device has been designed to fully support the PCI 2.1 specification and
provides plug and play software capabilities. During power-up initialisation the PCI BIOS will detect
the card and assign a unique I/O address location and interrupt line. This ensures that there are no
resource conflicts on the PCI bus. Multiple cards are supported through this mechanism without the
need for address decode links.
The PLX device contains a standard type 00H configuration space header. The table below shows the
registers within this header which are required for configuration of the APCI-IB40.
Configuration Space Header
These registers can be accessed using PCI BIOS functions. Please contact Arcom control systems
customer support team (Tel: 01223 412428) for a copy of the PCI BIOS Specification if required.
Digital I/O
If an I/O line is to be used as an output, writing a 0 to the corresponding bit in the output register
will turn the output buffer on and it will sink current. This will force the output line to a logic 0.
When the software output enable feature is selected the output control latch must be written to with
01H before the outputs will be enabled.
Since each output has an open collector drive, each line can alternatively be configured as an input
by switching the output buffer OFF (Writing 1 to the corresponding bit in the output register) and
then driving the line either high or pulling it low via an external source.
For lines using the software output enable feature the power-up links can be used to set the outputs
to a defined state at power on. If the output buffers are permanently enabled the power up state can
not be guaranteed.
Page 2
2192-09099-000-000
J591 APCI-IB40
Offset
00-01H
02-03H
18-1BH
2C-2DH
2E-2FH
3CH
Register Name
Vendor ID
Device ID
Base Address Register
Subsytem Vendor ID
Subsystem ID
Interrupt Line
Description
ID of PCI device manufacturer
ID of PCI device
I/O base address assigned to card
ID of board manufacturer
ID of Board
Interrupt line assigned to device
Value
10B5H (PLX Technology)
9050H
0000xxxx
13ABH (ARCOM)
0591H (APCI-IB40)
0x
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