Electrical configuration of each digital I/O line:
Note:- If an I/O line is to be configured as an input, it is necessary that the power-up link for that
group of lines is set in the A position. This means that any lines to be used as outputs will be set
high, or OFF. A good rule is to keep the lines to be used as inputs and those to be used as outputs
in separate groups of eight I/O lines.
Timer/Counter
The APCI-IB40 contains an 8254 compatible timer/counter. This device contains three 16-bit
counters, each with its own clock input, gate input and output pin. The clock input to counter 0 is
driven from an on board frequency source which is selected by LK1 to be 1MHZ, 100KHZ or 10KHZ,
and the output can be used to generate an interrupt signal. The clock and gate inputs for the
remaining counters are derived from I/O lines 24-27, and the output signals are routed to I/O lines
16-17 via LK3-4.
As this device is compatible with the counter/timer used on a PC/AT motherboard programming
information can be found in most PC reference guides. A data sheet for this device can be obtained
from our customer support team if required (Tel: 01223 412428).
I/O Map
The APCI-IB40 uses an indexed I/O addressing scheme to access the on-board devices and special
function registers. Two consecutive I/O locations are required to implement this scheme, the base
address is used to set the index value and the base+1 address is used to access the device.
The I/O base address is set by the PCI BIOS during initialisation (refer to the PCI Bus section of this
manual for details). A PCI BIOS function call may be used to determine the base address once the
system has been initialised. Multiple boards may be used in a system as each will be given a unique
address.
Page 3
2192-09099-000-000
J591 APCI-IB40
Address
Base
Base
Base+1
Read/Write
Write
Read
Read/Write
Register Name
Index Register
Clear Interrupt
Data Register
Function
Write Index value
Read clears pending interrupt
Read/Write data to and from registers
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