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S2-LPS 数据表(PDF) 20 Page - STMicroelectronics |
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S2-LPS 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 73 page  Parameter Comment Min. Typ. Max. Unit Reset pulse width (Treset, figure below) 0.7 2 ms Power-on VDD slope 2.0 V/ms The following picture shows how the S2-LPS must be controlled, i.e. the SDN signal must be tied to VBAT pin in order to avoid two potential issues during the start-up phase: 1. A cross conduction can appear on the GPIO until an available command is present on it. 2. The ESD protection diode from the SDN pad can sink current from the external driver connected to the SDN. Also the SDN signal generates an internal signal (POC), which disables the digital I/Os when set to 1. Figure 7. Start-up phase Examples of possible connections Figure 8. Examples of possible connections for SDN pin 4.3 RF synthesizer A crystal connected to XIN and XOUT provides a clock signal to the frequency synthesizer. The allowed clock signal frequency is 26 MHz. As an alternative, an external clock signal feeds XIN for proper operation. In this option, XOUT can be left either floating or tied to ground. S2-LPS RF synthesizer DS13831 - Rev 1 page 20/73 |
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