PSD813F1 datasheet(21/120 Pages) STMICROELECTRONICS

21 / 120 page

Preliminary

PSD813F1-A

The

PSD813F1

Functional

Blocks

(cont.)

9.1.1.3.1 Instructions

An instruction is defined as a sequence of specific operations. Each received byte is

sequentially decoded by the PSD and not executed as a standard write operation. The

instruction is executed when the correct number of bytes are properly received and the time

between two consecutive bytes is shorter than the time-out value. Some instructions are

structured to include read operations after the initial write operations.

The sequencing of any instruction must be followed exactly. Any invalid combination of

instruction bytes or time-out between two consecutive bytes while addressing Flash

memory will reset the device logic into a read array mode (Flash memory reads like a ROM

device). An invalid combination or time-out while addressing the EEPROM block will cause

the offending byte to be interpreted as a single operation.

The PSD813F1 supports these instructions (see Table 9):

Flash memory:

t Erase memory by chip or sector

t Suspend or resume sector erase

t Program a byte

t Reset to read array mode

t Read Flash Identifier value

t Read sector protection status

EEPROM:

t Write data to OTP Row

t Read data from OTP Row

t Power down memory

t Enable Software Data Protect (SDP)

t Disable SDP

t Return from read OTP Row read mode or power down mode.

These instructions are detailed in Table 9. For efficient decoding of the instructions, the first

two bytes of an instruction are the coded cycles and are followed by a command byte or

confirmation byte. The coded cycles consist of writing the data AAh to address X555h

during the first cycle and data 55h to address XAAAh during the second cycle. Address

lines A15-A12 are don’t cares during the instruction write cycles. However, the appropriate

sector select signal (FSi or EESi) must be selected.

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