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CDCE72010 数据表(PDF) 13 Page - Texas Instruments |
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CDCE72010 数据表(HTML) 13 Page - Texas Instruments |
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13 / 70 page ![]() AC/DC CHARACTERISTICS (CONTINUED) CDCE72010 www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008 over the specified industrial temperature range of –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT LVPECL Hi Swing Output fclk Output frequency Open loop config. 0 1500 MHz LVPECL high-level VOH Load, see Figure 5 VCC – 1.11 VCC – 0.87 V output voltage LVPECL low-level output VOL Load, see Figure 5 VCC – 2.06 VCC – 1.73 V voltage Differential output |VOD| Load, see Figure 5 760 1160 mV voltage Reference to output VCXO at 491.52MHz, Output 1 is divide by 16 phase offset without and reference at 30.72MHz, M and N delays tpho (2) 14 ns using available delay are fixed to one value (set to 0), PFD: adjustment 240kHz, (M and N = 128) tpd(LH)/ Propagation delay time, Crosspoint to crosspoint, load, see Figure 5 3.4 ns tpd(HL) VCXO_IN to output Divide by 1 for all dividers 45 Divide by 16 for all dividers 50 tsk(o) (3) LVPECL output skew ps Divide by 1 for divider 1 2700 Divide by 16 for all other dividers Output capacitance on CO VCC = 3.3 V; VO = 0 V or VCC 5 pF Y0 to Y8 Output capacitance on CO VCC = 3.3 V; VO = 0 V or VCC 7 pF Y9 Power-down output IOPDH VO = VCC 25 µA current Power-down output IOPDL VO = 0V 5 µA current Duty cycle 45 55 % tr/tf Rise and fall time 20% to 80% of Voutpp 55 75 135 ps LVDS-TO-LVPECL Output skew between tskP_C LVDS and LVPECL Crosspoint to VCC/2 0.9 1.1 1.3 ns outputs LVCMOS-TO-LVPECL Output skew between tskP_C LVCMOS and LVPECL Crosspoint to VCC/2 –150 260 700 ps outputs(4) (1) All typical values are at VCC = 3.3 V, TA = 25°C. (2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS and LVPECL. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): CDCE72010 |
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