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CDCE72010 数据表(PDF) 21 Page - Texas Instruments

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部件名 CDCE72010
功能描述  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  70 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCE72010 数据表(HTML) 21 Page - Texas Instruments

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CDCE72010
www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 0: SPI Mode
SPI
RAM
POWER UP
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
BIT
Bit
CONDITION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
0
4
0
INBUFSELX
Reference Input
Primary and secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)
EEPROM
Buffers
XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive pin
5
1
INBUFSELY
6
2
PRISEL
When REFSELCNTRL is set to 1, the following settings apply:
If RAM Bits (2,3): 00 – No input buffer is selected/active
Reference Input
If RAM Bits (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down
EEPROM
Buffer
7
3
SECSEL
If RAM Bits (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered down
If RAM Bits (2,3): 11 – Auto Select (PRI then SEC).
When set to 0, PRI- or SEC-clock is selected, depending on bits 2 and 3
Divider START
8
4
VCXOSEL
(default)
EEPROM
DETERM-Block
When set to 1, VCXO/AUX-clock is selected, overwrites bits 2 and 3
Reference Select Control to select if the control of the reference is from the
internal bit in Register 0 RAM bits 2 and 3 or from the external select pin.
- When set to 0: the external pin REF_SEL takes over the selection between
Reference
PRI and SEC. Autoselect is not available.
9
5
REFSELCNTRL
Selection
EEPROM
- When set to 1: The external pin REF_SEL is ignored. The table in (Register 0
Control
<2 and 3> ) describes which reference input clock is selected and available
(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing
diagram.
10
6
DELAY_PFD0
PFD pulse width PFD bit 0
PFD
EEPROM
PFD pulse width PFD bit 1
11
7
DELAY_PFD1
12
8
CP_MODE
Selects 3V option [0] or 5V option [1]
EEPROM
Charge Pump
Determines which direction CP current will regulate (Reference Clock leads to
13
9
CP_DIR
EEPROM
Feedback Clock, Positive CP output current [0], Negative CP output current [1])
Switches the current source in the charge pump on when set to 1 (TI
14
10
CP_SRC
EEPROM
Test-GTME)
Charge Pump
15
11
CP_SNK
Diagnostics
Switches the current sink in the charge pump on when set to 1 (TI Test-GTME)
EEPROM
16
12
CP_OPA
Switches the charge pump op-amp off when set to 1 (TI Test-GTME)
EEPROM
17
13
CP_PRE
Preset charge pump output voltage to VCC_CP/2, on [1], off [0]
EEPROM
18
14
ICP0
CP current setting bit 0
EEPROM
19
15
ICP1
Charge Pump
CP current setting bit 1
EEPROM
20
16
ICP2
CP current setting bit 2
EEPROM
21
17
ICP3
CP current setting bit 3
EEPROM
22
18
RESERVED
EEPROM
23
19
RESERVED
EEPROM
Charge Pump
Enables the 12-k
Ω pull-down resistor at I_REF_CP pin when set to 1 (TI
24
20
IREFRES
EEPROM
Diagnostics
Test-GTME)
25
21
PECL0HISWING
Output 0
High output voltage swing in LVPECL mode if set to 1
EEPROM
26
22
CMOSMODE0PX
LVCMOS mode select for OUTPUT 0 positive pin.
Output 0
EEPROM
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
27
23
CMOSMODE0PY
28
24
CMOSMODE0NX
LVCMOS mode select for OUTPUT 0 negative pin.
Output 0
EEPROM
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
29
25
CMOSMODE0NY
RAM BITS
OUTPUT TYPE
30
26
OUTBUFSEL0X
Output 0
22
23
24
25
26
27
EEPROM
LVPECL
0
0
0
0
0
1
LVDS
0
1
0
1
1
1
31
27
OUTBUFSEL0Y
Output 0
LVCMOS
See Settings Above(1)
0
0
EEPROM
All Outputs Disabled
0
1
0
1
1
0
(1)
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): CDCE72010



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