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CDCE72010 数据表(PDF) 3 Page - Texas Instruments

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部件名 CDCE72010
功能描述  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  70 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCE72010 数据表(HTML) 3 Page - Texas Instruments

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PACKAGE
49
1
32
64
33
48
16
17
TopView
BottomView
CDCE72010
www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 is available in a 64-pin lead-free “green” plastic quad flatpack package with enhanced bottom
thermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64).
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5,8,11,14,19
22,25,28,31
3.3V supply for the output buffers. There is no internal connection between VCC and AVCC.
VCC
Power
34,37,40, and
It is recommended that each VCC uses its own supply filter.
43
VCC_PLL
4, 63
A. Power 3.3V PLL supply voltage for the PLL circuitry.
VCC_IN
57, 60
A. Power 3.3V reference input buffers and circuitry supply voltage.
VCC_VCXO
51, 54
A. Power 3.3V VCXO input buffer and circuitry supply voltage.
GND
32
Ground
Ground connected to thermal pad internally.
GND
PAD
Ground
Ground on thermal pad. See layout recommendations.
VCCA
48, 49
A. Power 3.3V for internal analog circuitry power supply
A.
GND_CP
2
Analog ground for charge pump
Ground
Charge pump power supply pin used to have the same supply as the external VCO/VCXO.
VCC_CP
64
A. Power
It can be set from 2.3V to 3.6V.
In SPI mode it is an open drain output and it functions as a master and in slave out as a
SPI_MISO
15
DO
serial control data output from the CDCE72010.
LVCMOS input, control latch enable for the Serial Programmable Interface (SPI), with
SPI_LE
45
I
hysteresis in SPI mode.
or CD1
In configuration default mode this pin becomes CD1.
SPI_CLK
LVCMOS input, serial control clock input for the SPI bus interface, with hysteresis. In
46
I
or CD2
configuration default mode this pin becomes CD2.
LVCMOS input, master out slave in as a serial control data input to CDCE72010 for the SPI
SPI_MOSI
44
I
bus interface. In configuration default mode this pin becomes CD3 and it should be tied to
or CD3
GND.
SPI MODE = H; when driven high or left unconnected, it defaults to SPI bus interface mode.
CD MODE = L; If tied low the device goes into configuration default mode which is
MODE_SEL
16
I
configured by CD1, CD2, CD3, and AUX_SEL (CTRL_LE, CTRL_CLK, and CTRL_MOSI).
In configuration default mode the device loads various configuration defaults from the
EEPROM into memory at start-up.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): CDCE72010



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