ADAQ8092BBCZ datasheet(2/30 Pages) AD

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Data Sheet

ADAQ8092

TABLE OF CONTENTS

analog.com

Rev. 0 | 2 of 30

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................1

Specifications........................................................ 3

Timing Specifications......................................... 5

Absolute Maximum Ratings...................................9

Thermal Resistance........................................... 9

Electrostatic Discharge (ESD) Ratings...............9

ESD Caution.......................................................9

Pin Configurations and Function Descriptions.....10

Full Data-Rate CMOS Output Mode.................10

Double Data-Rate CMOS Output Mode........... 12

Double Data-Rate LVDS Output Mode.............14

Typical Performance Characteristics................... 16

Terminology......................................................... 19

Integral Nonlinearity (INL)................................ 19

Differential Nonlinearity (DNL)..........................19

Offset Error (OE).............................................. 19

Offset Error Drift............................................... 19

Gain Error.........................................................19

Dynamic Range................................................19

Spurious-Free Dynamic Range (SFDR)...........19

Intermodulation Distortion (IMD)...................... 19

Signal-to-Noise Ratio (SNR)............................ 19

Signal-to-Noise-and-Distortion Ratio

(SINAD).......................................................... 19

Effective Number of Bits (ENOB)..................... 19

Common-Mode Rejection Ratio (CMRR)......... 19

Power Supply Rejection Ratio (PSRR)............ 19

Theory of Operation.............................................20

Circuit Information............................................ 20

Reference.........................................................20

Sense............................................................... 20

Analog Inputs................................................... 20

Low-Pass Filter.................................................20

Encode Input.................................................... 20

Clock Duty-Cycle Stabilizer.............................. 21

Output Modes...................................................21

Overflow Bit...................................................... 22

Phase Shifting the Output Clock...................... 22

Data Format..................................................... 22

Digital Output Randomizer............................... 22

Alternate Bit Polarity.........................................23

Digital Output Test Patterns..............................23

Output Disable..................................................23

Sleep Mode...................................................... 23

Nap Mode.........................................................23

Serial Programming Mode................................23

Parallel Programming Mode.............................24

Software Reset.................................................24

Power-Supply Decoupling................................ 24

Power-Up Sequencing..................................... 24

Serial Programming Mode Register Map............ 25

(Address 0x01)............................................... 25

(Address 0x03)............................................... 26

0x04).............................................................. 26

Applications Information...................................... 28

Outline Dimensions............................................. 30

Ordering Guide.................................................30

Evaluation Boards............................................ 30

REVISION HISTORY

7/2022—Revision 0: Initial Version

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