ADAQ8092BBCZ datasheet(21/30 Pages) AD

21 / 30 page

Data Sheet

ADAQ8092

THEORY OF OPERATION

analog.com

Rev. 0 | 21 of 30

analog signals and not be routed next to digital traces on the circuit

board.

There are two modes of operation for the encode inputs: differential

encode mode and single-ended encode mode.

Differential encode mode is recommended for sinusoidal, PECL,

or LVDS encode inputs. The encode inputs are internally biased

to 1.2 V through 10 kΩ equivalent resistance. The encode inputs

can be driven higher than VDD, and the common-mode range is

from 1.1 V to 1.6 V. In the differential encode mode, ENC− must

stay at least 200 mV above ground to avoid falsely triggering the

single-ended encode mode. For optimal jitter performance, ENC+

and ENC− must have fast rise and fall times.

Figure 28. Equivalent Encode Input for Differential Encode Mode

Single-ended encode mode is recommended for CMOS encode in-

puts. To select this mode, ENC− is connected to ground and ENC+

is driven with a square-wave encode input. ENC+ can be driven

higher than VDD so that 1.8 V to 3.3 V CMOS logic levels can be

used. The ENC+ threshold is 0.9 V. For optimal jitter performance,

ENC+ must have fast rise and fall times. If the encode signal is

turned off, connected to GND, or drops below approximately 500

kHz, the analog-to-digital core automatically enters nap mode.

Figure 29. Equivalent Encode Input for Single-Ended Encode Mode

CLOCK DUTY-CYCLE STABILIZER

For optimal performance, the encode signal must have a 50%

(±5%) duty cycle. If the optional clock duty-cycle stabilizer circuit is

enabled, the encode duty cycle can vary from 30% to 70% and the

duty-cycle stabilizer maintains a constant 50% internal duty cycle.

If the encode signal changes frequency, the duty-cycle stabilizer

circuit requires 100 clock cycles to lock onto the input clock. The

duty-cycle stabilizer is enabled by the timing register, Register A2

(serial programming mode), or by CS (parallel programming mode).

For applications where the sample rate needs to be changed quick-

ly, the clock duty-cycle stabilizer can be disabled. If the duty-cycle

stabilizer is disabled, ensure that the sampling clock has a 50%

(±5%) duty cycle. Do not use the duty-cycle stabilizer below 5

MSPS.

OUTPUT MODES

The ADAQ8092 has three different output modes that can be used.

The output mode is set by the output mode register, Register

A3 (serial programming mode), or by SCK (parallel programming

mode). Note that double data rate CMOS cannot be selected in the

parallel programming mode.

Full Data Rate CMOS Mode

The data outputs, overflow, and the data output clocks have CMOS

output levels. The outputs is powered by OVDD, which can range

from 1.1 V to 1.9 V, allowing 1.2 V through 1.8 V CMOS logic

outputs.

For optimal performance, the digital outputs must drive minimal

capacitive loads. If the load capacitance is larger than 10 pF, a

digital buffer must be used.

Double Data Rate CMOS Mode

In this mode, two data bits are multiplexed and output on each data

pin, which reduces the number of digital lines by 15, simplifying

board routing and reducing the number of input pins needed to

receive the data. The data outputs, overflow, and the data output

clocks have CMOS output levels. The outputs is powered by

OVDD, which can range from 1.1 V to 1.9 V, allowing 1.2 V through

1.8 V CMOS logic outputs. Note that the overflow for both ADC

channels is multiplexed onto OF2_1.

For optimal performance, the digital outputs must drive minimal

capacitive loads. If the load capacitance is larger than 10 pF, a

digital buffer must be used.

Double Data-Rate LVDS Mode

In this mode, two data bits are multiplexed and output on each

differential output pair. There are seven LVDS output pairs per ADC

channel for the digital output data. The overflow and the data output

clock each have an LVDS output pair. Note that the overflow for

ADAQ8092BBCZ 数据表(PDF) 21 Page - Analog Devices

ADAQ8092BBCZ 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表下载