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ST10F269 数据表(PDF) 64 Page - STMicroelectronics |
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ST10F269 数据表(HTML) 64 Page - STMicroelectronics |
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64 / 160 page  ST10F269 64/160 12.4 - PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L. P1L (FF04h / 82h) SFR Reset Value: --00h P1H (FF06h / 83h) SFR Reset Value: --00h DP1L (F104h / 82h) ESFR Reset Value: --00h DP1H (F106h / 83h) ESFR Reset Value: --00h 12.4.1 - Alternate Functions of PORT1 When a demultiplexed external bus is enabled, PORT1 is used as address bus. Note: Demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose I/O. The upper 4 pins of PORT1 (P1H.7...P1H.4) are used as capture input lines (CC27IO...CC24IO). During external accesses in demultiplexed bus modes PORT1 outputs the 16-bit intra-segment address as an alternate output function. During external accesses in multiplexed bus modes, when no BUSCON register selects a demultiplexed bus mode, PORT1 is not used and is available for general purpose I/O. 15 14 13 12 11 10 9876543210 -------- P1L.7 P1L.6 P1L.5 P1L4 P1L.3 P1L.2 P1L.1 P1L.0 RW RW RW RW RW RW RW RW 15 14 13 12 11 10 9876543210 -------- P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 P1H.1 P1H.0 RW RW RW RW RW RW RW RW P1X.y Port Data Register P1H or P1L Bit y 15 14 13 12 11 10 9 8 76543210 - - - - - - - - DP1L.7 DP1L.6 DP1L.5 DP1L.4 DP1L.3 DP1L.2 DP1L.1 DP1L.0 RW RW RW RW RW RW RW RW 15 14 13 12 11 10 9 8 76543210 - - - - - - - - DP1H.7 DP1H.6 DP1H.5 DP1H.4 DP1H.3 DP1H.2 DP1H.1 DP1H.0 RW RW RW RW RW RW RW RW DP1X.y Port Direction Register DP1H or DP1L Bit y DP1X.y = 0: Port line P1X.y is an input (high-impedance) DP1X.y = 1: Port line P1X.y is an output |
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