ST10F269 datasheet(14/160 Pages) STMICROELECTRONICS

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ST10F269

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4 - MEMORY ORGANIZATION

The memory space of the ST10F269 is configured

in a unified memory architecture. Code memory,

data

memory,

registers

and

I/O

ports

are

organized within the same linear address space of

16M Bytes. The entire memory space can be

accessed Byte wise or Word wise. Particular

portions of the on-chip memory have additionally

been made directly bit addressable.

Flash: 256K Bytes of on-chip Flash memory.

IRAM:

Bytes

on-chip

internal

RAM

(dual-port) is provided as a storage for data,

system stack, general purpose register banks and

code. A register bank is 16 Wordwide (R0 to R15)

and / or Bytewide (RL0, RH0, …, RL7, RH7)

general purpose registers.

XRAM: 10K Bytes of on-chip extension RAM

(single port XRAM) is provided as a storage for

data, user stack and code.

The XRAM is divided into 2 areas, the first 2K

Bytes named XRAM1 and the second 8K Bytes

named XRAM2, connected to the internal XBUS

and are accessed like an external memory in

16-bit demultiplexed bus-mode without wait state

or read/write delay (50ns access at 40MHz CPU

clock). Byte and Word accesses are allowed.

The

XRAM1

address

range

00’E000h

- 00’E7FFh if XPEN (bit 2 of SYSCON register),

and XRAM1EN (bit 2 of XPERCON register) are

set. If XRAM1EN or XPEN is cleared, then any

access in the address range 00’E000h - 00’E7FFh

will be directed to external memory interface,

using the BUSCONx register corresponding to

address matching ADDRSELx register

The

XRAM2

address

range

00’C000h

- 00’DFFFh if XPEN (bit 2 of SYSCON register),

and XRAM2 (bit 3 of XPERCON register are set).

If bit XRAM2EN or XPEN is cleared, then any

access

the

address

range

00’C000h

- 00’DFFFh will be directed to external memory

interface,

using

the

BUSCONx

corresponding to address matching ADDRSELx

As the XRAM appears like external memory, it

cannot be used as system stack or as register

banks. The XRAM is not provided for single bit

storage and therefore is not bit addressable.

SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of

address space is reserved for the special function

which are used to control and to monitor the

function of the different on-chip units.

CAN1: Address range 00’EF00h - 00’EFFFh is

reserved for the CAN1 Module access. The CAN1

is enabled by setting XPEN bit 2 of the SYSCON

XPERCON register. Accesses to the CAN Module

use demultiplexed addresses and a 16-bit data

bus (Byte accesses are possible). Two wait states

give an access time of 100ns at 40MHz CPU

clock. No tri-state wait states are used.

CAN2: Address range 00’EE00h - 00’EEFFh is

reserved for the CAN2 Module access. The CAN2

is enabled by setting XPEN bit 2 of the SYSCON

XPERCON register. Accesses to the CAN Module

use demultiplexed addresses and a 16-bit data

bus (Byte accesses are possible). Two wait states

give an access time of 100ns at 40MHz CPU

clock. No tri-state wait states are used.

In order to meet the needs of designs where more

memory is required than is provided on chip, up to

16M Bytes of external RAM and/or ROM can be

connected to the microcontroller.

Note

If one or the two CAN modules are used,

Port 4 cannot be programmed to output all

8 segment address lines. Thus, only 4

segment address lines can be used,

reducing the external memory space to 5M

Bytes (1M Byte per CS line).

Visibility of XBUS Peripherals

In order to keep the ST10F269 compatible with

the ST10C167 and with the ST10F167, the XBUS

peripherals can be selected to be visible and / or

accessible on the external address / data bus.

CAN1EN and CAN2EN bits of XPERCON register

must be set. If these bits are cleared before the

global

enabling

with

XPEN-bit

SYSCON

pins and interrupts are not occupied by the

peripheral, thus the peripheral is not visible and

not available. Refer to Chapter 20 - Special

Function Register Overview.

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