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ST10F269 数据表(PDF) 52 Page - STMicroelectronics

部件名 ST10F269
功能描述  16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM
PDF  160 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F269 数据表(HTML) 52 Page - STMicroelectronics

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Figure 15 : Block Diagram of GPT1
10.2 - GPT2
The GPT2 module provides precise event control
and time measurement. It includes two timers (T5,
T6) and a capture/reload register (CAPREL). Both
timers can be clocked with an input clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction
(up/down)
for
each
timer
is
programmable by software or may additionally be
altered dynamically by an external signal on a port
pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of
timer T6 which changes its state on each timer
overflow/underflow.
The state of this latch may be used to clock timer
T5, or it may be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionally be cleared after the capture
procedure. This allows absolute time differences
to be measured or pulse multiplication to be
performed without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3
inputs
T3IN
and/or
T3EUD.
This
is
advantageous when T3 operates in Incremental
Interface Mode.
Table
12
lists
the
timer
input
frequencies,
resolution and periods for each pre-scaler option
at 40MHz CPU clock. This also applies to the
Gated Timer Mode of T6 and to the auxiliary timer
T5 in Timer and Gated Timer Mode.
2
n n=3...10
2
n n=3...10
2
n n=3...10
T2EUD
T2IN
CPU Clock
CPU Clock
CPU Clock
T3IN
T4IN
T3EUD
T4EUD
T2
Mode
Control
T3
Mode
Control
T4
Mode
Control
GPT1 Timer T2
GPT1 Timer T3
GPT1 Timer T4
T3OTL
Reload
Capture
U/D
U/D
Reload
Capture
Interrupt
Request
Interrupt
Request
Interrupt
Request
T3OUT
U/D
Table 12 : GPT2 Timer Input Frequencies, Resolution and Period
fCPU = 40MHz
Timer Input Selection T5I / T6I
000b
001b
010b
011b
100b
101b
110b
111b
Pre-scaler factor
4
8
16
32
64
128
256
512
Input Freq
10MHz
5MHz
2.5MHz
1.25MHz
625kHz
312.5kHz
156.25kHz
78.125kHz
Resolution
100ns
200ns
400ns
0.8µs
1.6µs
3.2µs
6.4µs
12.8µs
Period maximum
6.55ms
13.1ms
26.2ms
52.4ms
104.8ms
209.7ms
419.4ms
838.9ms



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