ST10F269 datasheet(127/160 Pages) STMICROELECTRONICS

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ST10F269

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RP0H (F108h / 84h)

ESFR

Reset Value: --XXH

Notes:

1. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on each Port P0H pins

during reset, RP0H default value is "FFh".

2. These bits are set according to Port 0 configuration during any reset sequence.

3. RP0H is a read only register.

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CLKSEL

SALSEL

CSSEL

WRC

R 1 - 2

R 2

WRC 2

Write Configuration Control

‘0’: Pin WR acts as WRL, pin BHE acts as WRH

‘1’: Pins WR and BHE retain their normal function

CSSEL 2

Chip Select Line Selection (Number of active CS outputs)

0 0: 3 CS lines: CS2...CS0

0 1: 2 CS lines: CS1...CS0

1 0: No CS line at all

1 1: 5 CS lines: CS4...CS0 (Default without pull-downs)

SALSEL 2

Segment Address Line Selection (Number of active segment address outputs)

0 0: 4-bit segment address: A19...A16

0 1: No segment address lines at all

1 0: 8-bit segment address: A23...A16

1 1: 2-bit segment address: A17...A16 (Default without pull-downs)

CLKSEL 1 - 2

System Clock Selection

000: fCPU = 2.5 x fOSC

001: fCPU = 0.5 x fOSC

010: fCPU = 1.5 x fOSC

011: fCPU = fOSC

100: fCPU = 5 x fOSC

101: fCPU = 2 x fOSC

110: fCPU = 3 x fOSC

111: fCPU = 4 x fOSC

ST10F269 数据表(PDF) 127 Page - STMicroelectronics

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