ST10F269 datasheet(137/160 Pages) STMICROELECTRONICS

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ST10F269

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The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins

P0.15-13 (P0H.7-5).

21.4.3 - Clock Generation Modes

The Table 34 associates the combinations of these three bits with the respective clock generation mode.

Notes: 1. The external clock input range refers to a CPU clock range of 1...40MHz.

2. The maximum input frequency depends on the duty cycle of the external clock signal.

3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial

resistance of the crystal is less than 40

Ω. However, higher frequencies can be applied with an external clock source on pin XTAL1,

but in this case, the input clock signal must reach the defined levels VIL and VIH2..

Figure 67 : Generation Mechanisms for the CPU Clock

Table 34 : CPU Frequency Generation

P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1

Notes

fXTAL x 4

2.5 to 10MHz

Default configuration

fXTAL x 3

3.33 to 13.33MHz

fXTAL x 2

5 to 20MHz

fXTAL x 5

2 to 8MHz

fXTAL x 1

1 to 40MHz

Direct drive2

fXTAL x 1.5

6.66 to 26.66MHz

fXTAL x 0.5

2 to 80MHz

CPU clock via prescaler3

fXTAL x 2.5

4 to 16MHz

TCL TCL

fCPU

fXTAL

fCPU

fXTAL

Phase locked loop operation

Direct Clock Drive

TCL

fCPU

fXTAL

Prescaler Operation

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