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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST10F269 数据表(PDF) 155 Page - STMicroelectronics |
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ST10F269 数据表(HTML) 155 Page - STMicroelectronics |
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155 / 160 page  ST10F269 155/160 21.4.13 - External Bus Arbitration VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF Note: 1. Partially tested, guaranteed by design characterization. Notes: 1. The ST10F269 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t 64. Symbol Parameter Maximum CPU Clock = 40 MHz Variable CPU Clock 1/2TCL = 1 to 40 MHz Minimum Maximum Minimum Maximum t61 SR HOLD input setup time to CLKOUT 15 – 15 – ns t62 CC CLKOUT to HLDA high or BREQ low delay – 12.5 – 12.5 ns t63 CC CLKOUT to HLDA low or BREQ high delay – 12.5 – 12.5 ns t64 CC CSx release 1 – 15 – 15 ns t65 CC CSx drive -4 15 -4 15 ns t66 CC Other signals release 1 – 15 – 15 ns t67 CC Other signals drive -4 15 -4 15 ns Figure 79 : External Bus Arbitration (Releasing the Bus) t61 t63 t66 1) t64 1) 2) t62 3) CLKOUT HOLD HLDA BREQ Others CSx (P6.x) |
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