CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

8

®Copyright 2008 Cirrus Logic, Inc.

DS705PP2

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting

PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and

internally converted to PCM before processing.

The port has two independent slave-only clock domains. Each data input can be independently assigned to a

clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which

off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input

data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data

rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or

the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be

ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192

kHz S/PDIF transmitter (data with embedded clock on a single line).

Note: Only one S/PDIF transmitter pin is available in the 128-pin package.

modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external

clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed

enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for

booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the

SCP2_BSY# pin in the 128-pin package.

4.2.4 Parallel Control Port

data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin

package.

4.2.5 External Memory Interface

The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. The

memory controller supports up to 1 MB of Flash memory in 8-bit data bus-width mode or 2 MB in 16-bit data

bus-width mode.

4.2.6 GPIO

Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output,

an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,

active-low, or active-high.

4.2.7 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the

DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on

the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference

frequency and can be switched to use the PLL output after overlays have been loaded and configured, either

through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit

with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or

2:1.