CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

24

®Copyright 2008 Cirrus Logic, Inc.

DS705PP2

5.18 Switching Characteristics — DSD Slave Input Port

Figure 13. Direct Stream Digital - Serial Audio Input Timing

5.19 Switching Characteristics — Digital Audio Output Port

Parameter

Symbol

Min

Typ

Max

Unit

DSD_SCLK Pulse Width Low

78

-

-

ns

DSD_SCLK Pulse Width High

78

-

-

ns

DSD_SCLK Frequency

(64x Oversampled)

-

1.024

-

3.2

MHz

DSD_A / _B valid to DSD_SCLK rising setup time

20

-

-

ns

DSD_SCLK rising to DSD_A or DSD_B hold time

20

-

-

ns

DSD clock to data transition (Phase Modulation mode)

-20

-

20

ns

Parameter

Symbol

Min

Max

Unit

1. CS4953xx has two Digital Audio Output modules having similar signal names ending in 1 and 2. Both DAO ports

share a common MCLK but have independent SCLKs and LRCLKs.

40

-

ns

DAO_MCLK duty cycle1

-40

60

%

2. Master mode timing specifications are characterized, not production tested.

40

-

ns

DAO_SCLK duty cycle for Master or Slave mode2

-40

60

%

Master Mode (Output A1 Mode)2,3

3. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is

divided to produce DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an

input

-19

ns

4. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the

point at which the data is valid.

-8

ns

DAO_DATA[3:0] delay from DAO_SCLK transition4

-10

ns

5.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO_DATA[3..0] delay from DAO_SCLK transition4

15

ns