ST10R167 datasheet(23/63 Pages) STMICROELECTRONICS

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ST10R167

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XII - A/D CONVERTER

A10-bit A/D converter with 16 multiplexed input

channels and a sample and hold circuit is inte-

grated on-chip. The sample time (for loading the

capacitors) and the conversion time is program-

mable and can be adjusted to the external circuitry.

Overrun error detection/protection is controlled by

the ADDAT register. Either an interrupt request is

generated when the result of a previous conver-

sion has not been read from the result register at

the time the next conversion is complete, or the

next conversion is suspended until the previous

result has been read. For applications which

require less than 16 analog input channels, the

remaining channel inputs can be used as digital

input port pins. The AD converter

of the

ST10F168 supports different conversion modes :

– Single channel single conversion : the analog

level of the selected channel is sampled once

and converted. The result of the conversion is

stored in the ADDAT register.

–

Single channel continuous conversion : the

analog level of the selected channel is repeatedly

sampled and converted. The result of the conver-

sion is stored in the ADDAT register.

– Auto scan single conversion : the analog level

of the selected channels are sampled once and

converted. After each conversion the result is

stored in the ADDAT register. The data can be

transfered to the RAM by interrupt software

management or using the powerfull Peripheral

Event Controller data transfert.

– Auto scan continuous conversion : the ana-

log level of the selected channels are repeatedly

sampled and converted. The result of the con-

version is stored in the ADDAT register. The

data can be transfered to the RAM by interrupt

software management or using the powerfull

Peripheral Event Controller data transfert.

– Wait for ADDAT read mode : when using con-

tinuous modes, in order to avoid to overwrite

the result of the current conversion by the next

one, the ADWR bit of ADCON control register

must be activated. Then, until the ADDAT regis-

ter is read, the new result is stored in a tempo-

rary buffer and the conversion is on hold.

– Channel

injection

mode

when

using

continuous modes, a selected channel can be

converted in between

without

changing the

current operating mode. The 10 bit data of the

conversion are stored in ADRES field of

ADDAT2. The current continuous mode remains

active after the single conversion is completed.

The Table : 9 ADC sample clock and conversion

time shows the ADC unit conversion clock, sample

clock.

A complete conversion will take 14tCC +2 tSC +

4 TCL. This time includes the conversion it-self,

the sampling time and the time required to trans-

fer the digital value to the result register. For

example, at 25MHz of CPU clock, minimum com-

plete conversion time is 7.76

µs.

The A/D converter provides automatic offset and

linearity self calibration. The calibration operation

is performed in two ways:

– A full calibration sequence is performed after a

reset and lasts 1.6ms minimum (at 25MHz CPU

clock). During this time, the ADBSY flag is set to

indicate the operation. Normal conversion can

be performed during this time. The duration of

the calibration sequence is then extended by the

time consumed by the conversions.

Note : After a power-on reset, the total

unadjusted error (TUE) of the ADC might be

worse than

±2LSB (max. ±4LSB). During the full

calibration sequence, the TUE is constantly

improved until at the end of the cycle, TUE is

within the specified limits of

±2LSB.

– One calibration cycle is performed after each

conversion : each calibration cycle takes 4 ADC

clock cycles. These operation cycles ensure

constant updating of the ADC accuracy, com-

pensating changing operating conditions.

Note

1. See chapter XX.

2. tCC = TCL x 24.

Table 9 : ADC sample clock and conversion time

ADCTC

Conversion Clock tCC

ADSTC

Sample Clock tSC

TCL1 = 1/2 x fXTAL

At fCPU = 25MHz

TCL x 24

0.48

µs00

tCC

0.48

µs2

Reserved, do not use

tCC x2

0.96

µs2

TCL x 96

1.92

µs10

tCC x4

1.92

µs2

TCL x 48

0.96

µs11

tCC x8

3.84

µs2

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