ST10R167 datasheet(44/63 Pages) STMICROELECTRONICS

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ST10R167

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The real minimum value for TCL depends on the

jitter of the PLL. The PLL tunes FCPU to keep it

locked on FXTAL. The relative deviation of TCL is

the maximum when it is refered to one TCL

period. It decreases according to the formula and

to the Figure 12 given below. For

N periods of

TCL the minimum value is computed using the

corresponding deviation DN:

where

N = number of consecutive TCL periods

and 1

≤ N ≤ 40. So for a duration of 3 TCL periods

(N = 3):

= 4 - 3/15 = 3.8%

3TCLmin = 3TCLNOM x (1 - 3.8/100)

= 3TCLNOM x 0.962

3TCLmin = (57.72ns at fCPU = 25MHz)

This is especially important for bus cycles using

wait states and for the operation of timers, serial

interfaces, etc. For all slower operations and

longer periods (e.g. pulse train generation or

measurement,

lower

Baud

rates,

etc.)

the

deviation caused by the PLL jitter is negligible.

XX.4.7 - Memory cycle variables

The tables below use three variables which are derived from the BUSCONx registers and represent the

special characteristics of the programmed memory cycle. The following table describes how these

variables are to be computed.

TCL

MI N

TCL

NO M

100

-------------

–







4N 15

) %

[]

⁄

–

(

Figure 12 : Approximated maximum PLL jitter

Symbol

Description

Values

ALE Extension

TCL * <ALECTL>

Memory Cycle Time wait states

2TCL * (15 - <MCTC>)

Memory Tristate Time

2TCL * (1 - <MTTC>)

±1

±2

±3

±4

Max.jitter [%]

This approximated formula is valid for

≤ N ≤ 40 and 10MHz ≤ f

CPU ≤ 25MHz.

XX - ELECTRICAL CHARACTERISTICS (continued)

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