RHF1201

Application information

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7

Application information

The RHF1201 is a high speed analog to digital converter based on a pipeline architecture

and a 0.25 µm CMOS process to achieve the best performance in terms of linearity and

power consumption.

The pipeline structure consists of 11 internal conversion stages in which the analog signal is

fed and sequentially converted into digital data. Signal input is sampled on the rising edge of

the clock.

The first 10 stages of the conversion include at each stage, an analog to digital converter, a

digital to analog converter, a Sample and Hold, and an amplifier with a gain of 2. A 1.5 bit

conversion resolution is also performed at each stage. The final stage is simply a

comparator. Each resulting LSB-MSB couple is then time shifted to recover from the delay

caused by the conversion. Digital data correction completes the processing by recovering

from the redundancy of the (LSB-MSB) couple at each stage. The corrected data is output

through the digital buffers.

The advantages of such a converter reside in the combination of pipeline architecture and

the most advanced technologies. The highest dynamic performances are achieved while

consumption remains at the lowest level.

7.1

RHF1201 operating modes

Extra functionalities are provided to simplify the application board as much as possible. The

operation modes offered by the RHF1201 are described in the following table.

Data format select (DFSB)

output MSB. This can be of interest when performing some further signal processing.

Table 10.

RHF1201 operating modes

Inputs

Outputs

Analog input differential level

DFSB

OEB

SRC

OR

DR

Most significant

bit (MSB)

>

RANGE

H

L

X

H

CLK

D11

-RANGE

>

L

X

H

CLK

D11

RANGE>

H

L

X

L

CLK

D11

>

RANGE

L

L

X

H

CLK

D11 Complemented

-RANGE

>

L

L

X

H

CLK

D11 Complemented

RANGE>

>-RANGE

L

L

X

L

CLK

D11 Complemented

X

X

H

X

HZ

HZ

HZ

X

X

X

H

X

CLK

Low slew rate

X

X

X

L

X

CLK

High slew rate