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RHF1201 数据表(PDF) 5 Page - STMicroelectronics |
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RHF1201 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 18 page ![]() RHF1201 Timing characteristics 5/18 4 Timing characteristics Figure 3. Timing diagram Table 2. Timing table Symbol Parameter Test conditions Min Typ Max Unit FS Sampling frequency 0.5 50 MHz Tck Sampling clock cycle 20 2000 ns DC Clock duty cycle FS = 45 Msps 45 50 65 % TC1 Clock pulse width (high) 10 1800 ns TC2 Clock pulse width (low) 8 1800 ns Tod Data output delay (fall of clock to data valid) 10 pF load capacitance 4 5 6 ns Tpd Data pipeline delay 5.5 5.5 5.5 cycles Tdr Data ready delay after data change 0.5 cycles Ton Falling edge of OEB to digital output valid data 13 ns Toff Rising edge of OEB to digital output tri-state 13 ns TrD Data rising time SRC = 0 5 pF load capacitance 2.8 ns SRC = 1 5pF load capacitance 5.7 ns TfD Data falling time SRC = 0 5pF load capacitance 2ns SRC = 1 5pF load capacitance 4.3 ns N-3 N-2 N-1 N+4 N+5 N N+3 N+1 N+2 N+6 N-3 N-1 N-4 N-5 N-6 N-7 N-8 N-9 CLK OEB DR Tod Ton Toff Tpd + Tod HZ state N DATA OUT Tdr |
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