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RHF1201 数据表(PDF) 13 Page - STMicroelectronics |
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RHF1201 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 18 page ![]() RHF1201 Application information 13/18 7.4 Clock input The quality of your converter is very dependent on your clock input accuracy, in terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended. Further points to consider in your implementation are: ● The input signal must be square-shaped with sharp edges of less than 1 ns. ● At 45 Msps, the duty cycle must be between 45% and 65%; in any case, the high level duration of Clock must be longer than 10 ns. ● The clock power supplies must be independent from the ADC output supplies to avoid digital noise modulation on the output. ● When powered-on, the circuit needs several clock periods to reach its normal operating conditions. 7.5 Power consumption optimization The internal architecture of the RHF1201 makes it possible to optimize power consumption according to the sampling frequency of the application. For this purpose, an External Rpol resistor is placed between the IPOL pin and the analog Ground. Therefore, the total dissipation can be adjusted across all the sampling range 0.5 Msps to 50 Msps to fulfil the requirements of applications where power saving is a must. For low sampling frequency, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performance. Table 11 sums up the relevant data. 7.6 Layout precautions ● Use of dedicated ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. ● The separation of the analog signal from the digital output part is mandatory to prevent noise from coupling onto the input signal. ● Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. ● All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. ● Keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. ● Choose component sizes as small as possible (SMD). Table 11. Total power consumption optimization depending on Rpol value FS (Msps) 0.85 1.7 13.6 45 50 Rpol (kΩ) 100 70 35 24 18 Optimized power (mW) 44 47 60 93 100 |
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