ST14C02C

4/12

SCL

SDA

SCL

SDA

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

1

23

7

89

MSB

ACK

START

CONDITION

SCL

1

23

7

89

MSB

ACK

STOP

CONDITION

state. A STOP condition terminates communica-

tion between the memory and the bus master. A

STOP condition at the end of a Read command

forces the memory device into its standby state. A

STOP condition at the end of a Write command

triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc-

cessful data transfer. The bus transmitter, either

master or slave, will release the SDA bus after

Start Condition

START is identified by a high to low transition of

the SDA line while the clock, SCL, is stable in the

high state. A START condition must precede any

data transfer command. The memory continuously

monitors (except during a programming cycle) the

SDA and SCL lines for a START condition, and will

not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the

SDA line while the clock SCL is stable in the high

Note: 1. The most significant bit, b7, is sent first.

Device Code

RW

b7

b6

b5

b4

b3

b2

b1

b0

Device Select

1010000

RW