ST5092 datasheet(7/29 Pages) STMICROELECTRONICS

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propriate programmable register. CS- must return

high at the end of the 2nd byte.

To read-back status information from ST5092, the

first byte of the appropriate instruction is strobed

in during the first CS- pulse, as defined in Table

1. CS- must be set low for a further 8 CCLK cy-

cles, during which data is shifted out of the CO

pin on the falling edges of CCLK.

When CS- is high, CO pin is in the high imped-

ance Tri-state, enabling CO pins of several de-

vices to be multiplexed together.

Thus, to summarise, 2 byte READ and WRITE in-

structions may use either two 8-bit wide CS-

pulses or a single 16 bit wide CS- pulse.

I.8 Control channel access to PCM interface:

It is possible to access the B channel previously

selected in Register CR1 in the case of com-

panded code only.

A byte written into Control Register CR3 will be

automatically transmitted from DX output in the

following frame in place of the transmit PCM data.

A byte written into Control Register CR2 will be

automatically sent through the receive path to the

Receive amplifiers.

In order to implement a continuous data flow from

the Control MICROWIRE interface to a B chan-

nel, it is necessary to send the control byte on

each PCM frame.

A current byte received on DR input can be read

in the register CR2. In order to implement a con-

tinuous data flow from a B channel to MI-

CROWIRE interface, it is necessary to read regis-

ter CR2 at each PCM frame.

(non delayed timing)

(delayed timing)

MCLK

FORMAT 1

(non delayed timing)

(delayed timing)

XB2

MCLK

FORMAT 2

D93TL075

Figure 1: Digital Interface Format (*)

(*) Significant Only For Companded Code.

ST5092

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