SERIAL CONTROL PORT TIMING

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Frequency of CCLK

2.048

MHz

Period of CCLK high

160

ns

Period of CCLK low

160

ns

Rise Time of CCLK

50

ns

Fall Time of CCLK

50

ns

Hold Time, CCLK high to CS– low

10

ns

Setup Time, CS– low to CCLK high

50

ns

Setup Time, CI valid to CCLK high

50

ns

Hold Time, CCLK high to CI invalid

50

ns

Delay Time, CCLK low to CO

data valid

Load = 100 pF

80

ns

Delay Time, CS–low to CO data

valid

50

ns

Delay Time CS–high or 8th CCLK

low to CO high impedance

whichever comes first

10

80

ns

Hold Time, 8th CCLK high to

CS– high

100

ns

Set up Time, CS– high toCCLK high

100

ns

Note 5:

For the purpoes of this specification the following conditions apply:

b) Delay times are measured from the inputs signal valid to the output signal valid.

c) Setup times are measured from the data input valid to the clock input invalid.

d) Hold times are measured from the clock signal valid to the data input invalid.

°Cto 85°C;

°C ; all signalsare referencedto GND)

DIGITAL INTERFACES

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Input Low Voltage

All digital inputs

DC

AC

V

V

Input High Voltage

All digital inputs

DC

AC

V

V

Output Low Voltage

µA

0.1

0.4

V

V

Output High Voltage

µA

V

V

Input Low Current

Any digital input,

-10

10

µA

Input High Current

Any digital input,

-10

10

µA

Output Current in High

impedance (Tri-state)

-10

10

µA

A.C. TESTING INPUT, OUTPUT WAVEFORM

0.8VCC

0.2VCC

0.7VCC

0.3VCC

0.7VCC

0.3VCC

TEST POINTS

INTPUT/OUTPUT

D93TL077

a logic ”1”and 0.2VCC for a logic ”0 ”.

ST5092

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