ST5481

8/18

The host gets back the configuration of the device

either a low power device, either a high power

device

(max

power

parameter

higher

than

100mA). Being a high power device allows to set

on a wake up ability because looking for a line

signal detection consume more than 500uA

allowed for a low power device when in a suspend

state.

To adjust the maximum power consumption

parameter into the configuration descriptor, the

logical values present on pins CFG0, CFG1,

RPSM are used (see Table 1).

At power on, the digital regulator is immediately

ON and after 100

µs the analog regulator is

authorized to feed the internal oscillator.

– Initialization and clocks management.

– A HARDWARE PIN RESET is done through pin

NRESET (active low).

– A delay of 4.5ms is introduced before distribut-

ing the clocks to the internal functions.

– A USB HARDWARE RESET is done through

DP, DM pins. This reset affects the USB inter-

face, resetting the USB core state machines. It

does not affect the application (S interface, reg-

isters, fifos).

A USB SOFTWARE RESET is done through USB

bmRequest SET_DEFAULT. It brings the S

interface, application registers, application state

machines and fifos pointers to default state.

When the device goes out of SUSPEND_CLOCK

state, a delay of 4.5ms is introduced before

distributing the clocks to the internal functions.

When the device enters into a suspend mode due

to inactivity on USB bus, the oscillator is stopped

in order to save power except if FCONF(3) is

equal to 1.

Table 1 : Maximum Power Current and Wake up Ability Coding

Max Power

Current

High/Low

Power

Wake Up

Ability

CFG1

CFG0

RPSM

Bm Attributes

ROM add 27

Max Power

ROM add 28

100 mA

LO

NO

0

0

1

80

32

150 mA

HI

NO

0

1

1

80

96

150 mA

HI

YES

1

0

1

A0

96

250 mA

HI

YES

1

1

1

A0

F9

100 mA

LO

NO

0

0

0

C0

32

150 mA

HI

NO

0

1

0

C0

96

150 mA

HI

YES

1

0

0

E0

96

250 mA

HI

YES

1

1

0

E0

F9