ST63140 datasheet(32/86 Pages) STMICROELECTRONICS

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TIMERS (Continued)

Timer Operating Modes

the external TIMER pin is not available on

ST631xx devices, the only allowed operating mode

is the output mode that have to be selected by set-

ting to 1 bit 4 and by clearing to 0 bit 5 in the TSCR1

Timer 2.

Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On

this mode the timer prescaler is clocked by the

prescaler clock input (OSC/12). The user can se-

lect the desired prescaler division ratio through the

PS2/PS1/PS0 bits. When TCR count reaches 0, it

sets the TMZ bit in the TSCR.

The TMZ bit can be tested under program control

to perform timer functions whenever it goes high.

Bit D4 and D5 on TSCR2 (Timer 2) register are not

implemented.

Timer Interrupt

When the counter register decrements to zero and

the software controlled ETI (enable timer interrupt)

bit is set to one then an interrupt request associ-

ated to interrupt vector #3 (for Timer 1) and to inter-

rupt vector #4 (for Timer 2) is generated. When the

counter decrements to zero also the TMZ bit in the

TSCR register is set to one.

Figure 29. Timer Working Principle

Notes :

TMZ is set when the counter reaches 00h ; how-

ever, it may be set by writing 00h in the TCR regis-

ter or setting the bit 7 of the TSCR register. TMZ

bit must be cleared by user software when servic-

ing the timer interrupt to avoid undesired interrupts

when leaving the interrupt service routine. After re-

set, the 8-bit counter register is loaded to FFh while

the 7-bit prescaler is loaded to 7Fh , and the TSCR

stopped (PSI=0) and timer interrupt disabled.

A write to the TCR register will predominate over

the 8-bit counter decrement to 00h function, i.e. if a

write and a TCR register decrement to 00h occur

simultaneously, the write will take precedence, and

the TMZ bit is not set until the 8-bit counter reaches

00h again. The values of the TCR and the PSC

registers can be read accurately at any time.

ST63140,142,126,156

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