ST63140 datasheet(45/86 Pages) STMICROELECTRONICS

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The D/A macrocell contains four PWM D/A outputs

(31.25kHz repetition, DA0-DA3) with six bit resolu-

tion plus a 62.5kHz open-drain output pin (OUT1)

specially suited for multistandard chroma proces-

sors driving. Both the D/A and OUT1 functions can

be disabled by software allowing the DA0-DA3 and

OUT1 pins to be used as general purpose open-

drain output pins able to withstand signals with up

to 12V amplitude.

6-Bit D/A Converters

Each D/A converter of ST631xx is composed by

the following main blocks:

- pre-divider

- 6-bit counter

- data latches and compare circuits

The pre-divider uses the clock input frequency

(8MHz) and its output clocks the 6-bit free-running

counter. The data latched in the four registers

(E0h, E1h, E2h and E3h) control the four D/A out-

puts (DA0,1,2 and 3). When all zeros are loaded

the relevant output is an high logic level; all 1’s cor-

respond to a pulse with a 1/64 duty cycle and al-

most 100% zero level. A 7th bit (bit D6) is used to

enable the relevant D/A output; when zero, the D/A

is no longer enabled and it forces the output to

zero. If the other six bits are all zero then the output

is controlled only by the enable bit.

The repetition frequency is 32.5kHz and is related

to the 8MHz clock frequency. All D/A outputs are

open-drain with standard current drive capability

and able to withstand up to 12V.

62.5 kHz Output

This pin provides a 62.5 kHz signal with a 50% duty

cycle; the output is enabled by a dedicated enable

bit (E0h register bit 7). When the 62.5kHz fre-

quency is disabled then the output is controlled by

the OUT1 bit and the line can be used as general

purpose open-drain output (E1h bit 7). The OUT1

output is open-drain with standard current drive ca-

pability and able to withstand signals with up to

12V amplitude.

D/A and OUT1 Data/Control Registers

This paragraph deals with the description of D/A

and OUT1 data/control registers. Some bits of DA2

and DA3 data/control registers are used for exter-

nal interrupt enable and A/D reference voltage

shift, please refer to A/D and IR descriptions for ad-

ditional information.

Figure 48. 6-bit PWM D/A & 62.5kHz Output

Configuration

DA0-DA5. These are the 6 bits of the PWM digital

to analog converter . Undefined after reset.

DAE. This is the D/A 0 enablebit. If zero, the output of

the D/A is forced to zero; if one, the output of the D/A

dependson bits DA0..DA5. Undefinedafter reset.

FO1. This is the 62.5kHz frequency output/ OUT1

selection bit. If one, the OUT1 pin will give a

62.5kHz frequency; if zero the OUT1 pin can be

used as general purpose open-drain output and

the value present on the pin depends on the value

of OUT1 bit programmed in the DA1 data/control

6-BIT PWM D/A CONVERTER AND 62.5 kHz

OUTPUT FUNCTION

DA0

DA0 Data/Contr ol Registers

(E0h, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

DAE D/A Enable Bit

FO1 62.5 kHzSelection Bit

Figure 49. DA0 Data/Enable Register

ST63140,142,126,156

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