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ST63140 数据表(PDF) 56 Page - STMicroelectronics |
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ST63140 数据表(HTML) 56 Page - STMicroelectronics |
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56 / 86 page ![]() Column 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A0 01 01 010 101 01 0 101 A1 00 11 001 100 11 0 011 A2 00 00 111 100 00 1 111 A3 00 00 000 011 11 1 111 Page A5 A4 LINE 5 0 0 1 FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch 5 0 1 2 FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch 5 1 0 3 FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch 5 1 1 4 FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch 6 0 0 5 FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Notes: FT. The format character required for each line. Characters in columns 1 thru 15 are displayed. Ch. (Byte) Character (Index into OSD character generator) or space character AVAILABLE SCREEN SPACE Table 12. OSD RAM Map Emulator Remarks There are a few differences between emulator and silicon. For noise reasons, the OSD oscillator pins are not available: the internal oscillator cannot be disabled and replaced by an external coil. In the emulator, the Character Bank Select register can be written also with Global Enable bit set, while this is not allowed in the device. Application Notes 1 - The OSD character generator is composed of a dual port video ram and some circuitry. It needs two input signals VSYNC and HSYNC to syncron- ize its dedicated oscillator to the TV picture. It gen- erates 4 output signals, that can be used from the TV set to generate the characters on the screen. For instance, they can be used to feed the SCART plug, providing an adequate buffer to drive the low impedance (75 Ω) of the SCART inputs. 2 - The Core sees the OSD as a number of RAM locations (80) plus a certain number of control reg- isters (6). These 86 locations are mapped in two pages of the dynamic data ram address range (0h..3Fh). In page 5 (load 20h in the register 0E8h), there are 64 bytes of RAM, the ones of the first 4 rows (16 bytes each row, 15 characters per row maximum, plus an hidden leading formatcharacter). In page 6 (load 40h in register 0E8h), the 16 bytes of the fifth row (0..0Fh), and the 6 control registers (10h..14h,17h). 3 - The video RAM is a dual port ram. That means that it can be addressed either from the Core or from the OSD circuitry itself. To reduce the com- plexity of the circuitry, and thus its cost, some re- strictions have been introduced in the use of the OSD. a. The Core can Only write to any of the 86 loca- tions (either video RAM or control registers). b. The Core can Only write to any of the leading 85 locations when the OSD oscillator is OFF. Only the last location (control register 17h in page 6) can be addressed at any time. This is the Global Enable Register, which contains only the GE bit. If it is set, the OSD is on, if it is reset the OSD is off. 4 - The timing of the on/off switching of the OSD oscillator is the following: a. GE bit is set. The OSD oscillator will start on the next VSYNC signal. b. GE bit is reset. The OSD oscillator will be im- mediately switched off. ON-SCREEN DISPLAY (Continued) ® ST63140,142,126,156 52/82 |
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