ST6367 datasheet(14/84 Pages) STMICROELECTRONICS

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

MEMORY SPACES (Cont’d)

EEPROM Description

The data space of ST638x family from 00h to 3Fh

is paged as described in Table 5. 384 bytes of

EEPROM located in six pages of 64 bytes (pages

0,1,2,3,4 and 5, see Table 5).

Through the programming of the Data RAM Bank

bank or page leaving unaffected the way to ad-

dress the static registers. The way to address the

“dynamic” page is to set the DRBR as described in

Table 5 (e.g. to select EEPROM page 0, the

DRBR has to be loaded with content 01h, see

Data RAM/EEPROM/OSD RAM addressing for

additional information). Bits 0, 1 and 7 of the

DRBR are dedicated to the EEPROM.

The EEPROM pages do not require dedicated in-

structions to be accessed in reading or writing.

The EEPROM is controlled by the EEPROM Con-

trol Register (EECR=EAh). Any EEPROM location

can be read just like any other data location, also

in terms of access time.

To write an EEPROM location takes an average

time of 5 ms (10ms max) and during this time the

EEPROM is not accessible by the Core. A busy

flag can be read by the Core to know the EEPROM

status before trying any access. In writing the

EEPROM can work in two modes: Byte Mode

(BMODE) and Parallel Mode (PMODE). The

BMODE is the normal way to use the EEPROM

and consists in accessing one byte at a time. The

PMODE consists in accessing 8 bytes per time.

EEPROM Control Register (EECR)

Address: EAh - Read only/Write only

Reset Value:

D7. Not used

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

SB. WRITE ONLY. If this bit is set the EEPROM is

disabled (any access will be meaningless) and the

power consumption of the EEPROM is reduced to

the leakage values.

D5, D4. Reserved for testing purposes, they must

be set to zero.

PS. WRITE ONLY. Once in Parallel Mode, as

soon as the user software sets the PS bit the par-

allel writing of the 8 adjacent registers will start. PS

is internally reset at the end of the programming

procedure. Note that less than 8 bytes can be writ-

ten; after parallel programming the remaining un-

defined bytes will have no particular content.

PE. WRITE ONLY. This bit must be set by the user

program in order to perform parallel programming

(more bytes per time). If PE is set and the “parallel

start bit” (PS) is low, up to 8 adjacent bytes can be

written at the maximum speed, the content being

stored in volatile registers. These 8 adjacent bytes

can be considered as row, whose A7, A6, A5, A4,

A3 are fixed while A2, A1 and A0 are the changing

bytes. PE is automatically reset at the end of any

parallel programming procedure. PE can be reset

by the user software before starting the program-

ming procedure, leaving unchanged the EEPROM

registers.

BS. READ ONLY. This bit will be automatically set

by the CORE when the user program modifies an

EEPROM register. The user program has to test it

before any read or write EEPROM operation; any

attempt to access the EEPROM while “busy bit” is

set will be aborted and the writing procedure in

progress completed.

EN. WRITE ONLY. This bit MUST be set to one in

order to write any EEPROM register. If the user

program will attempt to write the EEPROM when

EN= “0” the involved registers will be unaffected

and the “busy bit” will not be set.

After RESET the content of EECR register will be

00h.

Notes: When the EEPROM is busy (BS=”1”) the

EECR can not be accessed in write mode, it is only

possible to read BS status. This implies that as

long as the EEPROM is busy it is not possible to

change the status of the EEPROM control register.

EECR bits 4 and 5 are reserved for test purposes,

and must never be set to “1”.

PSPE

BSEN

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