ST6367 datasheet(31/84 Pages) STMICROELECTRONICS

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

4.2 TIMERS

The ST638x devices offer two on-chip Timer pe-

ripherals consisting of an 8-bit counter with a 7-bit

programmable prescaler, thus giving a maximum

count of 2

15, and a control logic that allows config-

uration the peripheral operating mode. Figure 20

shows the Timer block diagram. The content of the

8-bit counters can be read/written in the Timer/

Counter registers TCR that are addressed in the

data space as RAM locations at addresses D3h

(Timer 1), DBh (Timer 2). The state of the 7-bit

prescaler can be read in the PSC register at ad-

dresses D2h (Timer 1) and DAh (Timer 2). The

control logic is managed by TSCR registers at D4h

(Timer 1) and DCh (Timer 2) addresses as de-

scribed in the following paragraphs.

The following description applies to all Timers. The

8-bit counter is decrement by the output (rising

edge) coming from the 7-bit prescaler and can be

loaded and read under program control. When it

decrements to zero then the TMZ (timer zero) bit in

the TSCR is set to one. If the ETI (enable timer in-

terrupt) bit in the TSCR is also set to one an inter-

rupt request, associated to interrupt vector #3 for

Timer 1 and #1 for Timer 2, is generated. The in-

terrupt of the timer can be used to exit the MCU

from the WAIT mode.

The prescaler decrements on rising edge. The

prescaler input is the oscillator frequency divided

by 12. Depending on the division factor pro-

grammed by PS2/PS1/PS0 (see Table 11) bits in

the TSCR, the clock input of the timer/counter reg-

ister is multiplexed to different sources. On divi-

sion factor 1, the clock input of the prescaler is

also that of timer/counter; on factor 2, bit 0 of pres-

caler register is connected to the clock input of

TCR.

This bit changes its state with the half frequency of

prescaler clock input. On factor 4, bit 1 of PSC is

connected to clock input of TCR, and so on. On di-

vision factor 128, the MSB bit 6 of PSC is connect-

ed to clock input of TCR. The prescaler initialize bit

(PSI) in the TSCR register must be set to one to al-

low the prescaler (and hence the counter) to start.

If it is cleared to zero then all of the prescaler bits

are set to one and the counter is inhibited from

counting.The prescaler can be given any value be-

tween 0 and 7Fh by writing to the related register

address, if bit PSI in the TSCR register is set to

one. The tap of the prescaler is selected using the

PS2/PS1/PS0 bits in the control register. Figure 21

illustrates the Timer working principle.

Figure 20. Timer Peripheral Block Diagram

DATABUS 8

8-BIT

COUNTER

PSC

STATUS/CONTROL

TMZ

ETI

TOUT

DOUT

PSI

PS2

PS1

PS0

SELECT

1 OF 8

LATCH

SYNCHRONIZATION

LOGIC

TIMER

INTERRUPT

LINE

VA00009

:12

fOSC

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