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ST6385 数据表(PDF) 24 Page - STMicroelectronics |
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ST6385 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 84 page  24/84 ST6365, ST6375, ST6385 ST6367, ST6377, ST6387 INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register Interrupt Option Register (IOR) Address: (C8h) - Write only Reset Value: X000XXXXb The Interrupt Option Register (IOR register, loca- tion C8h) is used to enable/disable the individual in- terrupt sources and to select the operating mode of the external interrupt inputs. This register can be ad- dressed in the Data Space as RAM location at the C8h address, nevertheless it is a write-only register that can not be accessed with single-bit operations. The operating modes of the external interrupt inputs associated to interrupt vectors #1 and #2 are se- lected through bits 5 and 6 of the IOR register. Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. Not used. EL1. This is the Edge/Level selection bit of inter- rupt #1. When set to one, the interrupt is generat- ed on low level of the related signal; when cleared to zero, the interrupt is generated on falling edge. The bit is cleared to zero after reset. ES2. This is the edge selection bit on interrupt #2. This bit is used on the ST638x devices with on- chip OSD generator for VSYNC detection. When this bit is se to one, the interrupt #2 is positive edge sensitive, when cleared to zero the negative edge sensitive interrupt is selected. GEN. This is the global enable bit. When set to one all interrupts are globally enabled; when this bit is cleared to zero all interrupts are disabled (ex- cluding NMI). D3 - D0. These bits are not used. 3.4.4 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure; the user can consider the interrupt as an asynchronous call procedure. As this is an asyn- chronous event the user does not know about the context and the time at which it occurred. As a result the user should save all the data space registers which will be used inside the interrupt routines. There are separate sets of processor flags for nor- mal, interrupt and non-maskable interrupt modes which are automatically switched and so these do not need to be saved. The following list summarizes the interrupt proce- dure (refer also to Figure 19*) – Interrupt detection – The flags C and Z of the main routine are ex- changed with the flags C and Z of the interrupt routine (resp. the NMI flags) – The value of the PC is stored in the first level of the stack - The normal interrupt lines are inhibit- ed (NMI still active) – The edge flip-flop is reset – The related interrupt vector is loaded in the PC. – User selected registers are saved inside the in- terrupt service routine (normally on a software stack) – The source of the interrupt is found by polling (if more than one source is associated to the same vector) – Interrupt servicing – Return from interrupt (RETI) – Automatically the ST638x core switches back to the normal flags (resp the interrupt flags) and pops the previous PC value from the stack Figure 19. Interrupt Processing Flow-Chart 70 - EL1 ES2 GEN --- - INSTRUCTION FETCH INSTRUCTION EXECUTE INSTRUCTION WAS THE INSTRUCTION A RETI ? ? CLEAR INTERRUPT MASK SELECT PROGRAM FLAGS “POP” THE STACKED PC ? CHECK IF THERE IS AN INTERRUPT REQUEST AND INTERRUPT MASK SELECT INTERNAL MODE FLAG PUSH THE PC INTO THE STACK LOAD PC FROM INTERRUPT VECTOR (FFC/FFD) SET INTERRUPT MASK NO NO YES IS THE CORE ALREADY IN NORMAL MODE? VA000014 YES NO YES |
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