ST6385 datasheet(41/84 Pages) STMICROELECTRONICS

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

SERIAL PERIPHERAL INTERFACE (Cont’d)

SPI Control Register 1 (SCR1)

Address: EBh - Write only

Reset Value: 00h

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

b7-b4. These bits are not used.

STR. This is Start bit for I2C BUS/S-BUS. This bit

is meaningless when STD/SPI enable bit is

cleared to zero. If this bit is set to one and STD/SPI

bit is also set to “1” then SPI Start generation, be-

fore beginning of transmission, is enabled. Set to

zero after reset.

STP. This is Stop bit for I2C BUS/S-BUS. This bit

is meaningless when STD/SPI enable bit is

cleared to zero. If this bit is set to one and STD/SPI

bit is also set to “1” then SPI Stop condition gener-

ation is enabled. STP bit must be reset when

standard protocol is used (this is also the default

reset conditions). Set to zero after reset.

STD, SPI Enable. This bit, in conjunction with S-

BUS/I

2C BUS bit, allows the SPI disable and will

select between I2C BUS/S-BUS and Standard

shift register protocols. If this bit is set to one, it se-

lects both I

2C BUS and S-BUS protocols; final se-

lection between them is made by S-BUS/I2C BUS

bit. If this bit is cleared to zero when S-BUS/I

BUS is set to “1” the Standard shift register proto-

col is selected. If this bit is cleared to “0” when S-

BUS/I

2C BUS is cleared to 0 the SPI is disabled.

Set to zero after reset.

S-BUS/I

2C BUS Selection. This bit, in conjunction

with STD/SPI bit, allows the SPI disable and will

select between I

2C BUS and S-BUS protocols. If

this bit is cleared to “0” when STD bit is also “0”,

the SPI interface is disabled. If this bit is cleared to

zero when STD bit is set to “1”, the I

2C BUS proto-

col will be selected. If this bit is set to “1” when

STD bit is set to “1”, the S-BUS protocol will be se-

lected. Cleared to zero after reset.

Table 12. SPI Mode Selection

SPI Control Register 2 (SCR2)

Address: ECh - Read/Write

Reset Value: 00h

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

b7-b4. These bits are not used.

TX/RX. Write Only. When this bit is set, current

byte operation is a transmission. When it is reset,

current operation is a reception. Set to zero after

reset.

VRY/S. Read Only/Write Only. This bit has two dif-

ferent functions in relation to read or write opera-

tion. Reading Operation: when STD and/or TRX

bits is cleared to 0, this bit is meaningless. When

bits STD and TX are set to 1, this bit is set each

time BSY bit is set. This bit is reset during byte op-

eration if real data on SDA line are different from

the output from the shift register. Set to zero after

reset. Writing Operation: it enables (if set to one)

or disables (if cleared to zero) the interrupt coming

from VSYNC pin. Undefined after reset. Refer to

OSD description for additional information.

ACN. Read Only. If STD bit (D1 of SCR1 register)

is cleared to zero this bit is meaningless. When

STD is set to one, this bit is set to one if no Ac-

knowledge has been received. In this case it is au-

tomatically reset when BSY is set again. Set to

zero after reset.

BSY. Read/Set Only. This is the busy bit. When a

one is loaded into this bit the SPI interface start the

transmission of the data byte loaded into SSDR

data register or receiving and building the receive

data into the SSDR data register. This is done in

accordance with the protocol, direction and start/

stop condition(s). This bit is automatically cleared

at the end of the current byte operation. Cleared to

zero after reset.

Note: The SPI shift register is also the data trans-

mission register and the data received register;

this feature is made possible by using the serial

structure of the ST638x and thus reducing size

and complexity.

----

STR

STP

STD/

SPI

S-BUS/

CBUS

STD/SP

S-BUS/I

2C BUS

SPI Function

Disabled

STD Shift Reg.

I2C BUS

S-BUS

TX/RX VRY/S

ACN

BSY

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