ST70137 datasheet(13/22 Pages) STMICROELECTRONICS

13 / 22 page

ST70137

13/22

TEST CONDITION

All Ouputs have been loaded with.

* See text scheme at page 20.

CFG_MEM INTERFACE

CFG_SCE

Chip Enable

This pin is designed to directly interface to a serial

EEPROM that use the 93C66 EEPROM interface proto-

col. This pin has to be connected directly to the

EEPROM’s chip select pin.

CFG_SCK/GPO[ 6]

Serial Clock or General Purpose Output Pin 6 depending

on the internal selection. The selection is performed writ-

ing the proper bit inside the PCFW or UCFW register. At

the power-on or hardware reset the CFG_CLK functional-

ity is selected. This pin is designed to directly interface to

a serial EEPROM that use the 93C66 EEPROM interface

protocol.

CFG_SDI

Serial Data Input

Data going into this pin has to be generated on the rising

edge of CFG_SCK. This pin is designed to directly inter-

face to a serial EEPROM that use the 93C66 EEPROM

interface protocol.

CFG_SDO/GPO[ 7]

Serial Data/Address Outp ut

General Purpose Output Pin 7 depending on the internal

selection. The selection is performed writing the proper bit

inside the PCFW or UCFW register. At the power-up or

hardware reset the CFG_SDO functionality is selected.

The CFG_SDO data change is synchronous with the fall-

ing edge of CFG_SCK. This pin is designed to directly

interface to a serial EEPROM that use the 93C66

EEPROM interface protocol.

JTAG INTERFACE

TDI

JTAG Test Data Input.

TDO

JTAG Test Data Output.

TMS

JTAG Test Mode Select.

TCK

JTAG Test Clock.

TRSTB

JTAG Reset (active Low).

Outputs

Minimum

Maximum

Unit

PCI

USB *

Others

Signal Name

Direction

Init Status

Polarity

Signal Description

PIN DESCRIPTION (continued)

ST70137 数据表(PDF) 13 Page - STMicroelectronics

ST70137 数据表(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

数据表下载