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ST70137 数据表(PDF) 18 Page - STMicroelectronics |
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ST70137 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 22 page ![]() ST70137 18/22 PCI Clock Waveform 5V PCI Clock Waveform 3.3V PCI Timings * PCI REQN and GNTN are point-to-point signals and have different output valid delay and input setupt times than do bused signals. REQN has set up of 12ns and GNTN of 10ns. All other signals are bused. ** Guaranted by design. Symbol Parameter Minimum Typical Maximum Units Tval Clock to Signal Valid Delay (bused signals) 2 11 ns Tval(ptp) Clock to Signal Valid Delay (point to point) 2 12 ns Ton Float to Active Delay 2 ns Toff Active to Float Delay 28 ns Tsu Input Set up Time to Clock (bused signals) 7 ns Tsu(ptp) Input Set up Time to Clock (point to point) * 10, 12 * ns Th Input Hold Time from Clock 0 ns Trst Reset Active Time after Power Stable 1 ms Trst-clk Reset Active Time after CLK Stable ** 100 µs Trst-off Reset Active to Output Float Delay ** 40 ns 2.0V 1.5V 0.8V 2.4V 0.4V Tc Th TI 0.5VDD 0.4VDD 0.3VDD 0.6VDD 0.2VDD Tc Th TI |
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