ST72521 datasheet(208/211 Pages) STMICROELECTRONICS

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ST72521

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15.3 FLASH REV “S” AND ROM REV “W”

15.3.1 External clock source with PLL

External clock source is not supported with the

PLL enabled.

15.3.2 LVD Startup behaviour

When the LVD is enabled, the MCU reaches its

authorized operating voltage from a reset state.

However, in some devices, the reset state is re-

leased when VDD is approximately between 0.8V

and 1.5V. As a consequence, the I/Os may toggle

when VDD is within this window.

This may be an issue especially for applications

where the MCU drives power components.

Because Flash write access is impossible within

this window, the Flash memory contents will not be

corrupted.

Figure 125. LVD Startup Behaviour

15.3.3 I/O Port D Configuration

When using an external quartz crystal or ceramic

resonator, the fOSC2 clock may be disturbed be-

cause the device goes into reserved mode control-

led by Port D.

This happens with either one of the following con-

figurations:

– PD[3:1]=010 while CSS and PLL options are

both disabled and PD4 is toggling

– PD[4:1]=1010 while CSS or PLL options are en-

abled

This is detailed in the following table:

As a consequence, for cycle-accurate operations,

these configurations are prohibited in either input

or output mode.

Workaround:

To avoid this occurring, it is recommended to con-

nect one of these pins to GND (PD2 or PD4) or

VDD (PD1 or PD3).

15.4 FLASH Rev “S” DEVICES ONLY

15.4.1 LVD Operation

Depending on the operating conditions, especially

the VDD ramp up speed and ambient temperature,

in some cases the LVD may not start. When this

occurs, the MCU may operate outside the guaran-

teed functional area (see datasheet Figure 76)

without being forced into reset state.

In this case, proper use of the watchdog may

make it possible to recover through a watchdog re-

set and allow normal operations to resume.

Consequently, the LVD function is not guaranteed

in the current silicon revision. For complete securi-

ty, an external reset circuit must be added.

1.5V

VIT+

0.8V

LVD RESET

V D

Window

CSS

PLL PD[3:1]

PD4

Clock

Disturbance

OFF

010

Tog-

gling

Max. 2 clock cy-

cles lost at each

rising or falling

edge of PD4

xON

010

Max. 1 clock cy-

cle lost out of

every 16

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