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ST7538 数据表(PDF) 7 Page - STMicroelectronics |
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ST7538 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 30 page  7/30 ST7538 Voltage Regulator VDC Linear Regulator Output Voltage -25<Tj<125 C 0<Io<100mA 4.9 5.05 5.2 V -25<Tj<125 C 0<Io<150mA 4.7 5.2 V Line Regulation 7.5V<PAVcc<12.5V Idc=10mA 10 50 mV Load Regulation 5mA<Idc<100mA Vin=7.5V 20 75 mV I(VDC) Linear Regulator Current Limitation 150 180 210 V UVLO Input Under Voltage Lock Out Threshold 3.7 3.9 4.1 V UVLOHYS UVLO Hysteresis 340 mV PG Power Good Output Voltage Threshold on VDC pin 4.3 4.5 4.7 V PGHYS PG Hysteresis 250 mV Other Functions TRSTO Reset Time See Figure 18; Xtal=16MHz 50 ms TWD Watch-dog Pulse Width See Figure 18 3.5 ms TWM Watch-dog Pulse Period See Figure 18 TWD + 3.5 1490 ms TWO Watch-dog Time Out See Figure 18 1.5 s TOUT TX TIME OUT Control Register Bit 7 and Bit 8 See Figure 17 1 3 s TOFF Time Out OFF Time See Figure 17 125 ms TOFFD RxTx 0->1 vs. TOUT Delay See Figure 17 20 µs TCD Carrier Detection Time selectable by register Control Register bit 9 and bit10 Figure 10 500 1 3 5 µs ms ms ms TDCD CD_PD Propagation Delay Figure 10 300 500 µs MCLK Master Clock Output Selectable by register Control Register bit 15 and bit 16 see table 6 fclock fclock/2 fclock/4 MHz BAUD Baud rate Control Register bit 3 and bit 4 see table 6 600 1200 2400 4800 Baud TB Baud rate Bit Time (=1/BAUD) Control Register bit 3 and bit 4 see table 6 1667 833 417 208 µs Zero Crossing Detection ZCDEL Zero Crossing Detection delay (delay between the ZCIN and ZCOUT signals) Figure 19 1 µs ELECTRICAL CHARACTERISTCS (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit |
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