19/30

ST7538

Table 5. Vout vs. R1 & R2 resistors value

Notes: The rate of R2 takes in account the input resistance on the SENSE pin (36 K

Ω).

5.6nF capacitor effect has been neglected.

Figure 14. Typical Output Current vs. Rcl

s

Integrated Power Line Interface (PLI)

The Power Line Interface (PLI) is a double CMOS AB Class Power Amplifier with the two outputs

(ATOP1 and ATOP2) in opposition of phase.

Two are the possible configuration:

- Single Ended Output (ATOP1).

- Bridge Connection

The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each

individual Output. This topology virtually eliminates the even harmonics generation.

The PLI requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. PAVcc

Voltage must fulfil the following formula to work without clipping phenomena:

To allow the driving of an external Power Line Interface, the output of the ALC is available even on ATO

pin. ATO output has a current capability much lower than ATOP1 and ATOP2.

Vout (Vrms)

Vout (dB

µV)

(R1+R2)/R2

R2 (K

Ω)

R1 (K

Ω)

0.150

103.5

1.1

7.5

1.0

0.250

108.0

1.9

5.1

3.9

0.350

110.9

2.7

3.6

5.6

0.500

114.0

3.7

3.3

8.2

0.625

115.9

4.7

3.3

11.0

0.750

117.5

5.8

2.7

12.0

0.875

118.8

6.6

2.0

11.0

1.000

120.0

7.6

1.6

10.0

1.250

121.9

9.5

1.6

13.0

1.500

123.5

10.8

1.6

15.0

100

125

150

175

200

225

250

275

300

325

Irms

(mA)

2

2.5

3

3.5

Rcl(K

Ω)

D01IN1311

4

4.5

5

PAVcc

VATOP AC

()

2

------------------------------------

7.5V

+

≥