ST7538

12/30

– Synchronous mode.

St7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/T

line.

When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are

stable on CLR/T rising Edge.

When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD

line on CLR/T rising Edge.

line is forced Low. After Tcc time the modem starts providing received data on RxD line.

circuitry is switched on. (figure 3). After Tcc time the modem starts transmitting data present on TXD line

(figure 3) .

Figure 2.

Figure 3. Data Reception -> Data Transmission -> Data reception

PACKET MODE (Only for Reception)

In Packet mode data transmission from ST7538 to Host Controller is done at a higher speed than the

Mains one. This function could reduce the efficiency of data exchange process because the Host Control-

ler is involved in data reception for a shorter period of time.

To achieve this function is enabled an internal auxiliary buffer which stores the incoming bits. The buffer

is transferred to the host controller when full at the packet rate. The packet rate is programmable and is

related to the Mclk clock frequency. The length of the packet can be also programmed through the control

register (see table 9) to be 16, 14, 9 or 8 bits.

The packet mode to start working needs two levels of enable. One at the control register level the other at

the pin level. TxD is the pin that if forced High enables the Packet Mode Function. According to when TxD

is forced high, the next incoming bit is stored inside the internal buffer or delivered on RxD pin. If TxD pin

is forced low during a RX session the transceiver starts working in bit mode and the content of the packet

buffer is deleted.

Transmitting Bit Synchronization

CLR/T

RxD

CLR/T

TxD

Receiving Bit Synchronization

D03IN1416

CLR_T

RXD

RxTx

TXD

REG_DATA

D03IN1402

BIT23

BIT22