ST7LITE0 datasheet(52/122 Pages) STMICROELECTRONICS

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ST7LITE0, ST7SUPERLITE

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12-BIT AUTORELOAD TIMER (Cont’d)

11.2.3 Functional Description

PWM Mode

This mode allows a Pulse Width Modulated sig-

nals to be generated on the PWM0 output pin with

minimum core processing overhead. The PWM0

output signal can be enabled or disabled using the

OE0 bit in the PWMCR register. When this bit is

set the PWM I/O pin is configured as output push-

pull alternate function.

Note: CMPF0 is available in PWM mode (see

PWM0CSR description on page 55).

PWM Frequency and Duty Cycle

The PWM signal frequency (fPWM) is controlled by

the counter period and the ATR register value.

fPWM = fCOUNTER / (4096 - ATR)

Following the above formula, if fCPU is 8 MHz, the

maximum value of fPWM is 4 Mhz (ATR register

value = 4094), and the minimum value is 2 kHz

(ATR register value = 0).

Note: The maximum value of ATR is 4094 be-

cause it must be lower than the DCR value which

must be 4095 in this case.

At reset, the counter starts counting from 0.

Software must write the duty cycle value in the

DCR0H and DCR0L preload registers. The

DCR0H register must be written first. See caution

below.

When a upcounter overflow occurs (OVF event),

the ATR value is loaded in the upcounter, the

preloaded Duty cycle value is transferred to the

Duty Cycle register and the PWM0 signal is set to

a high level. When the upcounter matches the

DCRx value the PWM0 signals is set to a low level.

To obtain a signal on the PWM0 pin, the contents

of the DCR0 register must be greater than the con-

tents of the ATR register.

The polarity bit can be used to invert the output

signal.

The maximum available resolution for the PWM0

duty cycle is:

Resolution = 1 / (4096 - ATR)

Note: To get the maximum resolution (1/4096), the

ATR register must be 0. With this maximum reso-

lution and assuming that DCR=ATR,

a 0% or

100% duty cycle can be obtained by changing the

polarity .

Caution: As soon as the DCR0H is written, the

compare function is disabled and will start only

when the DCR0L value is written. If the DCR0H

write occurs just before the compare event, the

signal on the PWM output may not be set to a low

level. In this case, the DCRx register should be up-

dated just after an OVF event. If the DCR and ATR

values are close, then the DCRx register shouldbe

updated just before an OVF event, in order not to

miss a compare event and to have the right signal

applied on the PWM output.

Figure 34. PWM Function

DUTY CYCLE

AUTO-RELOAD

4095

000

WITH OE0=1

AND OP0=0

(ATR)

(DCR0)

WITH OE0=1

AND OP0=1

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