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ST7LITE2 数据表(PDF) 32 Page - STMicroelectronics |
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ST7LITE2 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 131 page ![]() ST7LITE2 32/131 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.3 Low Power Modes 7.6.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The CRSR register is frozen. The AVD remains active. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No 1 |
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