N

°

Symbol

Parameter

Value (Note)

Unit

OSCIN Divided

By 2

OSCIN Not Divided

By 2

Min. Max.

1

TdBR (BACK)

BREQ

↓ to BUSACK ↓

TpC+8

TwCL+12

50

ns

TpC(6P+2W+7)+65

TpC(3P+W+3)+TwCL+65

360

ns

2

TdBR (BACK)

BREQ

↑ to BUSACK ↑

3TpC+60

TpC+TwCL+60

185

ns

3

TdBACK (BREL)

BUSACK

↓ toBus

Release

20

20

20

ns

4

TdBACK (BACT)

BUSACK

↑ to Bus

Active

20

20

20

ns

Note: The value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period,

prescale value and number of wait cycles inserted.

The value right hand two columns show the timing minimum and maximum for an external clock at 24MHz divided by 2, prescale value of zero

and zero wait status.

INTCLK = 12MHz, Push-pull output configuration, unless otherwise specified)

Note : MEMINT = Group of memory interface signals: AS, DS, R/W, P00-P07, P10-P17

BUS REQUEST/ACKNOWLEDGE TIMING

®

ST9040

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