ST9040 datasheet(52/56 Pages) STMICROELECTRONICS

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In addition there is an 8 channel Analog to Digital

Converter with integral sample and hold, fast 11

µs

conversion time and 8 bit resolution. An Analog

Watchdog feature is included for two input chan-

nels.

Completing the device is a full duplex Serial Com-

munications Interface with an integral 110 to

375000 baud rate generator, asynchronous and

1.5Mbyte/s synchronous capability (fully program-

mable format) and associated address/wake-up

option, plus two DMA channels.

1.2 PIN DESCRIPTION

AS.

Address Strobe (output, active low, 3-state).

Address Strobe is pulsed low once at the begin-

ning of each memory cycle. The rising edge of AS

indicates that address, Read/Write (R/W), and

Data Memory signals are valid for program or data

memory transfers. Under program control, AS can

be placed in a high-impedance state along with

Port 0 and Port 1, Data Strobe (DS) and R/W.

DS. Data Strobe (output, active low, 3-state). Data

Strobe provides the timing for data movement to or

from Port 0 for each memory transfer. During a

write cycle, data out is valid at the leading edge of

DS. During a read cycle, Data In must be valid prior

to the trailing edge of DS. When the ST90R40 ac-

cesses on-chip Data memory, DS is held high dur-

ing the whole memory cycle. It can be placed in a

high impedance state along with Port 0, Port 1, AS

and R/W.

R/W. Read/Write (output, 3-state). Read/Write de-

termines the direction of data transfer for memory

transactions. R/W is low when writing to program

or data memory, and high for all other transactions.

It can be placed in a high impedance state along

with Port 0, Port 1, AS and DS.

RESET. Reset (input, active low). The ST9 is ini-

tialised by the Reset signal. With the deactivation

of RESET, program execution begins from the Pro-

gram memory location pointed to by the vector

contained in program memory locations 00h and

01h.

OSCIN, OSCOUT. Oscillator (input and output).

These pins connect a parallel-resonant crystal

(24MHz maximum), or an external source to the

on-chip clock oscillator and buffer. OSCIN is the in-

put of the oscillator inverter and internal clock gen-

erator; OSCOUT is the output of the oscillator

inverter.

AVDD. Analog VDD of the Analog to Digital Con-

verter.

AVSS. Analog VSS of the Analog to Digital Con-

verter.

Must be tied to VSS.

VDD. Main Power Supply Voltage (5V

±10%)

VSS. Digital Circuit Ground.

AD0-AD7, (P0.0-P0.7) Address/Data Lines (In-

put/Output, TTL or CMOS compatible). 8 lines pro-

viding a multiplexed address and data bus, under

control of the AS and DS timing signals.

A8-A15 Address Lines (Output, TTL or CMOS

compatible). 8 lines providing non-multiplexing ad-

dress bus, under control of the AS and DS timing

signals.

P2.0-P2.7 P3.0-P3.7, P4.0-P4.7, P5.0-P5.7, P7.0-

P7.7 I/O Port Lines (Input/Output, TTL or CMOS

compatible). 40 lines grouped into I/O ports of 8

bits, bit programmable under program control as

general purpose I/O or as Alternate functions (see

next section).

1.2.1 I/O PORT ALTERNATE FUNCTIONS

Each pin of the I/O ports of the ST90R40 may as-

sume software programmable Alternative Func-

tions as shown in the Pin Configuration Drawings.

Table 2 shows the Functions allocated to each I/O

Port pins.

GENERAL DESCRIPTION (Continued)

ST90R40

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