ST92F124 datasheet(30/426 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - DEVICE ARCHITECTURE

2 DEVICE ARCHITECTURE

2.1 CORE ARCHITECTURE

The ST9 Core or Central Processing Unit (CPU)

features a highly optimised instruction set, capable

of handling bit, byte (8-bit) and word (16-bit) data,

as well as BCD and Boolean formats; 14 address-

ing modes are available.

Four independent buses are controlled by the

Core: a 16-bit Memory bus, an 8-bit Register data

bus, an 8-bit Register address bus and a 6-bit In-

terrupt/DMA bus which connects the interrupt and

DMA controllers in the on-chip peripherals with the

Core.

This multiple bus architecture affords a high de-

gree of pipelining and parallel operation, thus mak-

ing the ST9 family devices highly efficient, both for

numerical calculation, data handling and with re-

gard to communication with on-chip peripheral re-

sources.

2.2 MEMORY SPACES

There are two separate memory spaces:

– The Register File, which comprises 240 8-bit

registers, arranged as 15 groups (Group 0 to E),

each containing sixteen 8-bit registers plus up to

64 pages of 16 registers mapped in Group F,

which hold data and control bits for the on-chip

peripherals and I/Os.

– A single linear memory space accommodating

both program and data. All of the physically sep-

arate memory areas, including the internal ROM,

internal RAM and external memory are mapped

in this common address space. The total ad-

dressable memory space of 4 Mbytes (limited by

the size of on-chip memory and the number of

external address pins) is arranged as 64 seg-

ments of 64 Kbytes. Each segment is further

subdivided into four pages of 16 Kbytes, as illus-

trated in Figure 18. A Memory Management Unit

uses a set of pointer registers to address a 22-bit

memory field using 16-bit address-based instruc-

tions.

2.2.1 Register File

The Register File consists of (see Figure 19):

– 224 general purpose registers (Group 0 to D,

registers R0 to R223)

– 6 system registers in the System Group (Group

E, registers R224 to R239)

– Up to 64 pages, depending on device configura-

tion, each containing up to 16 registers, mapped

to Group F (R240 to R255), see Figure 20.

Figure 18. Single Program and Data Memory Address Space

3FFFFFh

3F0000h

3EFFFFh

3E0000h

20FFFFh

02FFFFh

020000h

01FFFFh

010000h

00FFFFh

000000h

Address

16K Pages

64K Segments

up to 4 Mbytes

Data

Code

255

254

253

252

251

250

249

248

247

21FFFFh

210000h

133

134

135

Reserved

132

ST92F124 数据表(PDF) 30 Page - STMicroelectronics

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