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ST92F124 数据表(PDF) 6 Page - STMicroelectronics |
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ST92F124 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 426 page  6/426 ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 2. ST92F124V1: Architectural Block Diagram 256 bytes Register File RAM 4 Kbytes ST9 CORE 8/16 bits CPU Interrupt Management RCCU Ext. MEM. ADDRESS DATA Port0 Ext. MEM. ADDRESS Ports 1,9 WATCHDOG AS DS RW WAIT NMI DS2 RW MISO MOSI SCK SS A[10:8] A[21:11] A[7:0] D[7:0] ST. TIMER SPI SDA SCL I2C BUS FLASH 128 Kbytes WDOUT HW0SW1 STOUT Fully Prog. I/Os P0[7:0] P1[7:3] P1[2:0] P2[7:0] P3[7:4] P3[3:1] P4[7:4] P4[3:0] P5[7:0] P6[5:2,0] P6.1 P7[7:0] P8[7:0] P9[7:0] MF TIMER 0 TINPA0 TOUTA0 TINPB0 TOUTB0 TINPA1 TOUTA1 TINPB1 TOUTB1 INT[6:0] WKUP[15:0] MF TIMER 1 E3 TM 1 Kbyte OSCIN OSCOUT RESET CLOCK2/8 INTCLK CK_AF ADC AVDD AVSS AIN[15:8] AIN[7:0] EXTRG VREG VOLTAGE REGULATOR The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7, Port8 and Port9. ICAPA0 OCMPA0 ICAPB0 OCMPB0 EXTCLK0 ICAPA1 OCMPA1 ICAPB1 OCMPB1 EXTCLK1 EF TIMER 0 EF TIMER 1 SCI M TXCLK RXCLK SIN DCD SOUT CLKOUT RTS SCI A RDI TDO 9 |
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