ST92F124 datasheet(33/426 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - DEVICE ARCHITECTURE

2.3 SYSTEM REGISTERS

The System registers are listed in Table 6. They

are used to perform all the important system set-

tings. Their purpose is described in the following

pages. Refer to the chapter dealing with I/O for a

description of the PORT[5:0] Data registers.

Table 6. System Registers (Group E)

2.3.1 Central Interrupt Control Register

Please refer to the ”INTERRUPT” chapter for a de-

tailed description of the ST9 interrupt philosophy.

CENTRAL INTERRUPT CONTROL REGISTER

(CICR)

R230 - Read/Write

Reset Value: 1000 0111 (87h)

Bit 7 = GCEN: Global Counter Enable.

This bit is the Global Counter Enable of the Multi-

function Timers. The GCEN bit is ANDed with the

CE bit in the TCR Register (only in devices featur-

ing the MFT Multifunction Timer) in order to enable

the Timers when both bits are set. This bit is set af-

ter the Reset cycle.

Note: If an MFT is not included in the ST9 device,

then this bit has no effect.

Bit 6 = TLIP: Top Level Interrupt Pending.

This bit is set by hardware when a Top Level Inter-

rupt Request is recognized. This bit can also be

set by software to simulate a Top Level Interrupt

Request.

0: No Top Level Interrupt pending

1: Top Level Interrupt pending

Bit 5 = TLI: Top Level Interrupt bit.

0: Top Level Interrupt is acknowledged depending

on the TLNM bit in the NICR Register.

1: Top Level Interrupt is acknowledged depending

on the IEN and TLNM bits in the NICR Register

(described in the Interrupt chapter).

Bit 4 = IEN: Interrupt Enable .

This bit is cleared by interrupt acknowledgement,

and set by interrupt return (iret). IEN is modified

implicitly by iret, ei and di instructions or by an

interrupt acknowledge cycle. It can also be explic-

itly written by the user, but only when no interrupt

is pending. Therefore, the user should execute a

instruction (or guarantee by other means that

no interrupt request can arrive) before any write

operation to the CICR register.

0: Disable all interrupts except Top Level Interrupt.

1: Enable Interrupts

Bit 3 = IAM: Interrupt Arbitration Mode.

This bit is set and cleared by software to select the

arbitration mode.

0: Concurrent Mode

1: Nested Mode.

Bits 2:0 = CPL[2:0]: Current Priority Level.

These three bits record the priority level of the rou-

tine currently running (i.e. the Current Priority Lev-

el, CPL). The highest priority level is represented

by 000, and the lowest by 111. The CPL bits can

be set by hardware or software and provide the

reference according to which subsequent inter-

rupts are either left pending or are allowed to inter-

rupt the current interrupt service routine. When the

current interrupt is replaced by one of a higher pri-

ority, the current priority value is automatically

stored until required in the NICR register.

R239 (EFh)

SSPLR

R238 (EEh)

SSPHR

R237 (EDh)

USPLR

R236 (ECh)

USPHR

R235 (EBh)

MODE REGISTER

R234 (EAh)

PAGE POINTER REGISTER

R233 (E9h)

R232 (E8h)

R231 (E7h)

FLAG REGISTER

R230 (E6h)

CENTRAL INT. CNTL REG

R229 (E5h)

PORT5 DATA REG.

R228 (E4h)

PORT4 DATA REG.

R227 (E3h)

PORT3 DATA REG.

R226 (E2h)

PORT2 DATA REG.

R225 (E1h)

PORT1 DATA REG.

R224 (E0h)

PORT0 DATA REG.

GCE

TLIP

TLI

IEN

IAM

CPL2 CPL1 CPL0

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